Senior Physical Design Engineer

Astera Labs; Santa Clara (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

Astera Labs is seeking a Senior Physical Design Engineer to lead design processes for connectivity ASICs used by top cloud service providers. The ideal candidate will have a strong background in electrical engineering and experience in timing closure and backend methodologies for complex silicon products. Join a team that values creativity and diversity in thought, and play a key role in the development of innovative solutions for modern data-driven applications.

Qualifications

• At least 3 years of experience in SoC/silicon product development.
• Hands-on knowledge of backend tools for 7nm technologies or less.
• Good scripting skills in tcl, python or Perl.

Responsibilities

• Oversee planning, coordination, and execution in design.
• Develop/maintain timing constraints and methodologies.
• Drive design from architecture to GDSII, ensuring delivery.

Skills

Communication

Problem Solving

Team Collaboration

Entrepreneurial Mindset

Education

Bachelor's in Electrical Engineering or Computer Engineering

Master's degree (preferred)

Tools

Cadence

Synopsys

DFT Tools

Job description

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications atwww.asteralabs.com .

As an Astera Labs Senior Physical Design Engineer (STA) you will play a crucial role in overseeing the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. To accomplish that, you will work closely with designers, verification engineering, and engineering operations. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE / Computer is required, and a Master’s degree is preferred.
• ≥3 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block and full-chip level.
• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of System Verilog/Verilog.
• Experience with DFT tools and techniques.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in tcl, python or Perl.

Preferred Experience:

• Good knowledge of design for test (DFT), stuck-at and transition scan test insertion.
• Familiarity with DFT test coverage and debug.
• Familiarity with ECO methodologies and tools.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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