Senior Photonic Process Integration & Foundry Liaison

COHERENT; Fremont (CA); Hybrid; USD 190,000 - 262,000; Full time

Job summary

Coherent Corp. is seeking a senior-level engineer to serve as the primary technical liaison with external silicon photonics and advanced packaging foundries in Fremont, CA. You will drive process development, qualification, audits, and CAPA initiatives across multiple foundry platforms.

You will lead root-cause analyses, monitor yield metrics, and implement CIP and DFx/DFY strategies in collaboration with PIC design teams, reliability, and manufacturing. Hybrid work options apply.

Qualifications

• PhD in Electrical Engineering, Physics, Materials Science, or related field.
• 10+ years of semiconductor foundry experience.
• Strong knowledge of photonics foundry and back-end manufacturing processes.
• Experience with qualification of photonic foundry process and PIC products.
• Experience with advanced packaging.

Responsibilities

• Serve as the primary technical liaison between Coherent and external silicon photonics, silicon CMOS, and advanced packaging foundry partners.
• Coordinate and drive foundry engagements related to process development, process control, manufacturing readiness, and technology qualification.
• Plan, coordinate, and participate in technical and quality audits of external foundry and manufacturing partners to assess process controls, quality systems, manufacturing readiness, and continuous improvement initiatives.
• Lead root-cause investigations and failure analysis activities in collaboration with foundries, internal reliability teams, and product engineering organizations.
• Track, analyze, and resolve wafer-level, die-level, and module-level yield detractors through systematic data analysis and corrective action implementation.
• Partner with foundries to identify, prioritize, and execute CIP initiatives that improve device performance, yield, reliability, and manufacturability.
• Collaborate with PIC design teams to identify process sensitivities and implement DFM/DFY and robustness improvements.
• Develop process characterization plans and monitor key process metrics, process windows, and critical device parameters across multiple foundry platforms.
• Analyze fabrication, test, and reliability data to identify process trends, excursions, and opportunities for improvement.
• Support new product introductions, technology transfers, process qualifications, and foundry migrations.
• Work closely with reliability, test engineering, and manufacturing teams to establish process control methodologies and monitor long-term process stability.
• Participate in technical reviews with internal stakeholders and external foundry partners and communicate project status, risks, and mitigation plans.
• Drive CAPA resulting from yield excursions, reliability concerns, or customer-return investigations.
• Evaluate foundry process control methodologies, SPC implementation, excursion management procedures, change control practices, and CAPA systems.
• Review foundry process changes, ECNs, PCNs, and technology updates to assess potential impacts on product performance, yield, reliability, and qualification status.
• Establish and maintain supplier performance metrics, including yield, defect density, process capability, cycle time, on-time delivery, and quality indicators.
• Develop and maintain process integration documentation, manufacturing specifications, process control plans, and supplier quality requirements.

Skills

Silicon photonics

SPC analysis

Failure analysis

Python data analysis

Foundry engagement

Education

PhD in Electrical Engineering, Physics, Materials Science, or related field

10+ years semiconductor foundry experience

Tools

JMP

Job description

Coherent Corp. is seeking a senior-level engineer to serve as the primary technical liaison with external silicon photonics and advanced packaging foundries in Fremont, CA. You will drive process development, qualification, audits, and CAPA initiatives across multiple foundry platforms.

You will lead root-cause analyses, monitor yield metrics, and implement CIP and DFx/DFY strategies in collaboration with PIC design teams, reliability, and manufacturing. Hybrid work options apply.