Senior Photonic Link Co-Designer (Electro-Optic)

Lightmatter; Mountain View (CA); Hybrid; USD 180,000 - 240,000; Full time

Benefits offered by this job

Comprehensive Health Care Plan

Retirement Savings Matching

Equity grants

Paid Time Off

Job summary

Lightmatter is pioneering AI data center photonics. We seek a Sr. Staff Engineer to own end-to-end simulation, co-design, and verification of photonic-electronic links in Passage, from device modeling to silicon channel characterization.

You will work with photonic device physics, high-speed analog/digital interfaces, and co-simulation tools to improve link margin and power efficiency while partnering with device and circuit teams across challenging topologies.

Qualifications

• PhD in Electrical Engineering, Applied Physics, Physics, or related photonics/optics with 5+ years of experience; or MS with 8+ years of relevant photonics experience.
• Deep expertise in silicon photonics devices and system-level optical link design.
• Hands-on photonic simulation experience using industry tools.

Responsibilities

• Develop and improve electro-optic link simulation models from device to channel BER.
• Build multi-physics co-design models integrating optical and electrical domains.
• Perform corner analyses, Monte Carlo, and PVT studies to bound link margin and drive design actions.

Skills

Photonic device physics

Photonic simulation

Analog/mixed-signal co-simulation

Python scripting

Strong communication

Education

PhD in EE/Applied Physics/photons

MS + 8 years relevant experience

Tools

VPI Photonics

Lumerical INTERCONNECT/FDTD

Cadence Virtuoso/Spectre

Verilog-A

Keysight ADS

Python

Job description

Lightmatter is pioneering AI data center photonics. We seek a Sr. Staff Engineer to own end-to-end simulation, co-design, and verification of photonic-electronic links in Passage, from device modeling to silicon channel characterization.

You will work with photonic device physics, high-speed analog/digital interfaces, and co-simulation tools to improve link margin and power efficiency while partnering with device and circuit teams across challenging topologies.