Senior Photonic Layout & Tape-Out Lead

Acceler8 Talent

Berkeley (CA)

On-site

USD 198,000 - 242,000

Full time

19 hours ago
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Job summary

Acceler8 Talent in Berkeley is seeking a Senior Photonic Layout & Design Flow Engineer to own the PIC layout and tape-out workflow, bridging photonics and electronic design teams. You will lead Cadence-based photonic design flows and drive integration of photonic components into full chip layouts.

Ideal candidates will have hands-on leadership with a track record of commercial PIC layout and tape-out, experience with DRC/LVS, PDKs, and foundry submission, and an ability to coordinate PIC and EIC

Qualifications

  • Experience owning a PIC layout and tape-out flow.
  • Proficient with Cadence Photonics or Cadence Virtuoso.
  • Experience with PDKs, layout, verification and sign-off.
  • Cross-functional PIC/EIC integration experience.
  • Ability to lead design workflows hands-on.

Responsibilities

  • Lead commercial PIC layout and tape-out.
  • Establish Cadence-based photonic design flows.
  • Integrate photonic components into chip layouts.
  • Work with photonic PDKs and foundry requirements.
  • Own DRC, LVS, sign-off and foundry submission.
  • Coordinate PIC and EIC engineers toward tape-out.
  • Identify and close layout, verification risks.
  • Guide designers while remaining hands-on.

Skills

PIC layout
Tape-out flow
Cadence Photonics
Cadence Virtuoso
PDK experience
Layout verification
Foundry submission
PIC-EIC integration
Design workflows

Tools

Cadence Photonics
Cadence Virtuoso

Job description

Acceler8 Talent in Berkeley is seeking a Senior Photonic Layout & Design Flow Engineer to own the PIC layout and tape-out workflow, bridging photonics and electronic design teams. You will lead Cadence-based photonic design flows and drive integration of photonic components into full chip layouts.

Ideal candidates will have hands-on leadership with a track record of commercial PIC layout and tape-out, experience with DRC/LVS, PDKs, and foundry submission, and an ability to coordinate PIC and EIC

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