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Acceler8 Talent in Berkeley is seeking a Senior Photonic Layout & Design Flow Engineer to own the PIC layout and tape-out workflow, bridging photonics and electronic design teams. You will lead Cadence-based photonic design flows and drive integration of photonic components into full chip layouts.
Ideal candidates will have hands-on leadership with a track record of commercial PIC layout and tape-out, experience with DRC/LVS, PDKs, and foundry submission, and an ability to coordinate PIC and EIC
Acceler8 Talent in Berkeley is seeking a Senior Photonic Layout & Design Flow Engineer to own the PIC layout and tape-out workflow, bridging photonics and electronic design teams. You will lead Cadence-based photonic design flows and drive integration of photonic components into full chip layouts.
Ideal candidates will have hands-on leadership with a track record of commercial PIC layout and tape-out, experience with DRC/LVS, PDKs, and foundry submission, and an ability to coordinate PIC and EIC