Photonic Layout Design Engineer

Acceler8 Talent; Berkeley (CA); On-site; USD 198,000 - 242,000; Full time

Job summary

Acceler8 Talent in Berkeley is seeking a Senior Photonic Layout & Design Flow Engineer to own the PIC layout and tape-out workflow, bridging photonics and electronic design teams. You will lead Cadence-based photonic design flows and drive integration of photonic components into full chip layouts.

Ideal candidates will have hands-on leadership with a track record of commercial PIC layout and tape-out, experience with DRC/LVS, PDKs, and foundry submission, and an ability to coordinate PIC and EIC

Qualifications

• Experience owning a PIC layout and tape-out flow.
• Proficient with Cadence Photonics or Cadence Virtuoso.
• Experience with PDKs, layout, verification and sign-off.
• Cross-functional PIC/EIC integration experience.
• Ability to lead design workflows hands-on.

Responsibilities

• Lead commercial PIC layout and tape-out.
• Establish Cadence-based photonic design flows.
• Integrate photonic components into chip layouts.
• Work with photonic PDKs and foundry requirements.
• Own DRC, LVS, sign-off and foundry submission.
• Coordinate PIC and EIC engineers toward tape-out.
• Identify and close layout, verification risks.
• Guide designers while remaining hands-on.

Skills

PIC layout

Tape-out flow

Cadence Photonics

Cadence Virtuoso

PDK experience

Layout verification

Foundry submission

PIC-EIC integration

Design workflows

Tools

Cadence Photonics

Cadence Virtuoso

Job description

Up to 220k base + equity

I’m working with a well-funded photonic computing startup building optical processors for next-generation AI workloads.

The company is developing an integrated platform spanning photonic and electronic ICs, packaging and system architecture. They are looking for a senior Photonic Layout & Design Flow Engineer to lead the complete PIC layout and tape-out workflow connecting the photonics and electronic design teams.

This is not a component-only design position. You’ll own the path from individual photonic designs to a complete, verified and foundry-ready chip-level layout.

You’ll work on problems such as:

• Leading commercial PIC layout and tape-out
• Establishing and improving Cadence-based photonic design flows
• Integrating photonic components into complete chip-level layouts
• Working with photonic PDKs and foundry-process requirements
• Owning DRC, LVS, sign-off and foundry submission
• Resolving PIC/EIC interfaces and shared design constraints
• Coordinating photonics and electronic IC engineers toward tape-out
• Identifying and closing layout, verification and integration risks

Looking for engineers who have:

• Personally owned a commercial PIC layout and tape-out flow
• Used Cadence Photonics, Cadence Virtuoso or a closely related commercial environment
• Experience with PDKs, physical layout, verification and sign-off
• Taken photonic designs through foundry submission
• Worked across PIC and EIC integration
• Built or improved design workflows rather than relying entirely on established handoffs
• The technical depth to guide other designers while remaining hands-on

Experience with GlobalFoundries’ silicon-photonics technology is particularly relevant, although closely transferable commercial-foundry experience can also be considered. Python-based photonics tools can complement the profile but should not be the candidate’s only design environment.

This is an opportunity to establish a foundational design capability and own a critical part of a new photonic computing platform.