Photonic Layout Design Engineer

Acceler8 Talent; Berkeley, Northern (CA, KY); Hybrid; USD 198,000 - 242,000; Full time

Job summary

Acceler8 Talent is seeking a Senior Photonic Layout & Design Flow Engineer to own the PIC layout and tape-out workflow, uniting photonics and electronic design teams across the development cycle.

You will lead Cadence photonics flows, work with PDKs and foundries, and drive DRC/LVS sign-off and successful submission while guiding designers hands-on toward reliable tape-outs.

Qualifications

• Senior-level photonics layout and tape-out experience.
• Experience with photonic PDKs and foundry constraints.
• Ability to guide designers while staying hands-on.

Responsibilities

• Leading commercial PIC layout and tape-out
• Establishing and improving Cadence-based photonic design flows
• Integrating photonic components into complete chip-level layouts
• Working with photonic PDKs and foundry-process requirements
• Owning DRC, LVS, sign-off and foundry submission
• Resolving PIC/EIC interfaces and design constraints
• Coordinating photonics and electronic IC engineers toward tape-out
• Identifying and closing layout, verification and integration risks

Skills

PIC layout

Cross-team collaboration

Hands-on leadership

Foundry processes

Tools

Cadence Photonics

Cadence Virtuoso

PDK experience

Foundry submission

Python-based photonics tools

Job description

Photonic Layout & Design Flow Engineer

On-site | Berkeley, CA | 5 days per week

Up to 220k base + equity

I’m working with a well-funded photonic computing startup building optical processors for next-generation AI workloads.

The company is developing an integrated platform spanning photonic and electronic ICs, packaging and system architecture. They are looking for a senior Photonic Layout & Design Flow Engineer to lead the complete PIC layout and tape-out workflow connecting the photonics and electronic design teams.

This is not a component-only design position. You’ll own the path from individual photonic designs to a complete, verified and foundry-ready chip-level layout.

You’ll work on problems such as:

• Leading commercial PIC layout and tape-out
• Establishing and improving Cadence-based photonic design flows
• Integrating photonic components into complete chip-level layouts
• Working with photonic PDKs and foundry-process requirements
• Owning DRC, LVS, sign-off and foundry submission
• Resolving PIC/EIC interfaces and shared design constraints
• Coordinating photonics and electronic IC engineers toward tape-out
• Identifying and closing layout, verification and integration risks

Looking for engineers who have:

• Personally owned a commercial PIC layout and tape-out flow
• Used Cadence Photonics, Cadence Virtuoso or a closely related commercial environment
• Experience with PDKs, physical layout, verification and sign-off
• Taken photonic designs through foundry submission
• Worked across PIC and EIC integration
• Built or improved design workflows rather than relying entirely on established handoffs
• The technical depth to guide other designers while remaining hands-on

Experience with GlobalFoundries’ silicon-photonics technology is particularly relevant, although closely transferable commercial-foundry experience can also be considered. Python-based photonics tools can complement the profile but should not be the candidate’s only design environment.

This is an opportunity to establish a foundational design capability and own a critical part of a new photonic computing platform.