Senior Performance Analytics Lead – Kernel & Platform

NVIDIA Gruppe; Santa Clara (CA); Hybrid; USD 272,000 - 489,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking an outstanding Performance Analysis Manager to lead an engineering team responsible for supervising and optimizing product performance across the full hardware lifecycle. You will bridge design-time predictions and real-world execution by evaluating performance from early simulation and emulation through post-silicon bring‑up to production hardware.

The role includes analyzing DSL-to-IR flows, setting expectation models, curating workload testlists, coordinating CUDA releases,

Qualifications

• MS or PhD in CS/CE/EE or equivalent experience.
• 10+ years in systems/software performance engineering.
• 5+ years leading technical engineering teams.
• Full lifecycle performance experience from design-time to production hardware.
• Proven ability to build and correlate performance models with telemetry.
• Understanding of DSLs, compiler flows (DSL -> IR -> target code).
• Experience with AI tooling for automation.

Responsibilities

• Lead end-to-end lifecycle performance tracking from pre-silicon to post-release."
• Architect performance models and correlate pre-silicon predictions with hardware telemetry.
• Analyze kernel authoring flows from DSLs to IRs and target hardware.
• Develop and maintain stress tests and workload testlists for regression detection.
• Coordinate CUDA release timing and performance targets.
• Promote workflow automation using AI tools for telemetry and reporting pipelines.

Skills

Performance modeling

Team leadership

Python automation

AI tooling

DSL & compiler flows

Education

MS or PhD in CS/CE/EE

Tools

MLIR

LLVM IR

Job description

NVIDIA is seeking an outstanding Performance Analysis Manager to lead an engineering team responsible for supervising and optimizing product performance across the full hardware lifecycle. You will bridge design-time predictions and real-world execution by evaluating performance from early simulation and emulation through post-silicon bring‑up to production hardware.

The role includes analyzing DSL-to-IR flows, setting expectation models, curating workload testlists, coordinating CUDA releases,