Senior Manager, Performance Engineering - Kernel and Software Platforms

Nvidia Corporation in; Santa Clara (CA); On-site; USD 272,000 - 489,000; Full time

Job summary

NVIDIA is seeking a Senior Manager, Performance Engineering to lead an engineering team responsible for supervising and optimizing product performance across the full hardware lifecycle.

The role bridges design-time predictions with real-world execution, evaluating performance from early simulation through post-silicon bring-up to production hardware, including kernel/IR flow analysis and CUDA release alignment.

Job description

Senior Manager, Performance Engineering - Kernel and Software Platforms (Finance)

NVIDIA's accelerated computing platform relies on continuous performance excellence at every stage of development. We are seeking an outstanding Performance Analysis Manager to lead an engineering team responsible for supervising and optimizing product performance throughout the full hardware lifecycle. In this role, you will bridge the gap between design-time predictions and real-world execution: evaluating performance from early simulation and emulation, through post-silicon bring-up, to production hardware and ongoing release support. Your role involves analyzing kernel authoring flows from DSLs to internal code representations. You will set expectation models, curate workload testlists, and coordinate with CUDA release schedules. Additionally, you will promote automation with AI tools such as Claude and Codex.

What you’ll be doing

• End-to-End Lifecycle Performance Tracking: Supervise and maintain continuous performance tracking for GPU software products from pre-silicon build time, simulation, and emulation environments through initial post-silicon validation, product hardware, and post-release maintenance.
• Expectation Modeling & Correlation: Architect theoretical and empirical performance models to set targets early in design. Continuously correlate pre-silicon simulation predictions against early hardware and production silicon to diagnose and eliminate discrepancies.
• DSL-to-IR Flow Analysis: Evaluate and benchmark performance translation across diverse kernel authoring flows-analyzing code efficiency from high-level DSLs (e.g., Triton, PyTorch) through compiler Intermediate Representations (IRs) down to target hardware execution across every phase of platform maturity.
• Workload Synthesis & Testlist Build: Identify, craft, and maintain stress-test suites and workload testlists representative of production applications. Use these testlists to stress system performance, detect regressions early in simulation, and validate hardware release candidates.
• CUDA Release Cadence Alignment: Work multi-functionally with compiler, architecture, and platform software teams to ensure performance achievements hit target expectations on schedules strictly linked to the CUDA release timeline.
• Workflow Automation Using Advanced Technology: Integrate modern AI infrastructure (e.g., Claude, OpenAI Codex, agentic LLM workflows) to automate telemetry analysis, root-cause pre-vs-post silicon performance deltas, and streamline performance reporting pipelines.

What we need to see

• MS or PhD in Computer Science, Computer Engineering, Electrical Engineering, or a related field, or equivalent experience.
• 10+ overall years of experience in systems/software performance engineering, platform benchmarking, or a related area.
• 5+ years of experience leading or managing technical engineering teams.
• Full Lifecycle Experience: Demonstrated track record tracking performance through the entire hardware pipeline-from design-time simulation/emulation infrastructure to early post-silicon bring-up and deployed production hardware.
• Performance Modeling & Telemetry: Proven track record to build expectation models and correlate simulation predictions with physical hardware telemetry without needing to be a daily low-level kernel developer.
• DSL & Compiler Pipeline Context: Understanding of modern kernel compilation pipelines, compiler flows (DSL -> IR -> target code), and how high-level software abstraction impacts low-level execution efficiency.
• Release & Testlist Management: Experience developing workload testlists to detect performance regressions and aligning performance delivery with major software release cycles (e.g., CUDA cadence).
• AI Tooling & Automation: Proficiency in Python automation with practical experience employing generative AI APIs/models (Codex, Claude, custom agents) to automate triage and analytical workflows.

Ways to stand out from the crowd

• Pre-Silicon Correlation Pipelines: Experience building automated "shift-left" performance validation frameworks that map pre-silicon simulator data directly against post-silicon measurements.
• Compiler Stack Insights: Hands-on analytical experience with intermediate representations (MLIR, LLVM IR, NVVM/PTX) to identify performance loss between abstraction layers.
• Agentic AI Triage: Proven success designing LLM-driven agents that automatically analyze performance regressions between hardware software releases and summarize root causes.

#LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 272,000 USD - 431,250 USD for Level 4, and 320,000 USD - 488,750 USD for Level 5.

You will also be eligible for equity and benefits .

Applications for this job will be accepted at least until August 11, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.