Senior GPU Kernel Architect & Optimizer

CoreWeave

Sunnyvale (CA)

On-site

USD 182,000 - 242,000

Full time

14 days+

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Benefits offered by this job

Medical–dental–vision insurance
401(k) with employer match
Flexible PTO
Company-paid Life Insurance
Tuition Reimbursement
Employee stock purchase program

Job summary

CoreWeave is seeking a Senior Engineer for the Benchmarking & Performance team to own CUDA kernel authoring and optimization for AI inference. You will write, profile, and tune kernels on the critical path of large‑scale model serving to maximize throughput and minimize latency.

You will collaborate with product, orchestration, and hardware teams to deliver end‑to‑end performance gains, drive reproducible benchmarks such as MLPerf, and mentor junior engineers while upholding high coding and

Qualifications

  • 5+ years in HPC, GPU software, or performance‑critical systems.
  • Hands‑on CUDA experience with kernel writing and optimization.
  • Deep understanding of GPU architecture, tensor cores, and memory hierarchy.
  • Strong C++ and Python coding skills; low‑level performance focus.
  • Familiarity with model serving stacks and kernel‑dominant costs.

Responsibilities

  • Author, profile, and optimize CUDA kernels on the critical path of large‑scale model serving.
  • Tune kernels for throughput and latency, leveraging tensor cores and memory optimizations.
  • Prototype using kernel‑authoring DSLs and maintain reproducible benchmarking workflows.
  • Lead design reviews, drive architecture within the team, and mentor juniors.
  • Ensure end‑to‑end performance gains across inference stacks and meet P99 SLAs.

Skills

CUDA kernels
C++
Python
GPU architecture
Performance tuning

Tools

Nsight Compute
Nsight Systems
MLPerf

Job description

CoreWeave is seeking a Senior Engineer for the Benchmarking & Performance team to own CUDA kernel authoring and optimization for AI inference. You will write, profile, and tune kernels on the critical path of large‑scale model serving to maximize throughput and minimize latency.

You will collaborate with product, orchestration, and hardware teams to deliver end‑to‑end performance gains, drive reproducible benchmarks such as MLPerf, and mentor junior engineers while upholding high coding and

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