Sr. PD Methodology Engineer, Annapurna Labs - Cloud Scale Machine Learning (AWS)

Amazon; Austin (TX); On-site; USD 159,200 - 215,300; Full time

Job summary

Annapurna Labs, part of AWS Utility Computing, is seeking a senior physical design engineer to define, develop, and deploy PD/verification methodologies (RTL2GDS) for ML accelerator chips in advanced nodes.

You will drive CAD flow optimizations for PPA and TAT, work with EDA vendors, tune cloud infrastructure, and interface with RTL, PD, and DFT teams to improve efficiency and QoR dashboards.

Qualifications

• 10+ years in physical design or CAD flow development.
• Experience with RTL2GDS and advanced node flows.
• Strong scripting in Python/Perl and C++.

Responsibilities

• Define, develop, and deploy PD/verification methods (RTL2GDS) for ML accelerator chips.
• Drive CAD flow optimizations for PPA and TAT improvements.
• Work with EDA tool vendors to evaluate methods and fix issues.
• Fine-tune cloud infrastructure to improve compute/storage utilization for PD.
• Coordinate with RTL, PD, Package, and DFT teams to improve methods.
• Troubleshoot digital tool flows and deploy scalable solutions.
• Create dashboards and reports for QoR and project tracking.
• Fluent in TCL, Python; build scalable flows for parallel design.

Skills

Python

Perl

C++

Scripting

EDA collaboration

Education

BS + 10 years in EE/CS

MS + 7 years in EE/CS

Tools

Innovus

ICC2

Fusion Compiler

STA

Sign-Off

Job description

Annapurna Labs, part of AWS Utility Computing, designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to tackle technical challenges that have never been seen before and deliver results that help our customers change the world.

Amazon Web Services provides a highly reliable, scalable, low‑cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world. We have data center locations in the U.S., Europe, Singapore, and Japan, and serve customers across all industries.

Key Job Responsibilities

• Define, develop, and deploy innovative physical design and verification methodologies (RTL2GDS) for ML Accelerator chips in advanced nodes.
• Drive optimizations in CAD flows/methodologies for PPA and TAT improvements.
• Work with EDA tool vendors to evaluate new methods, resolve bugs, and improve usability.
• Fine‑tune cloud infrastructure to improve compute and storage utilization for physical design work.
• Interface directly with RTL, Physical Design, Package Design, and DFT teams to improve methodologies and efficiencies.
• Independently troubleshoot digital tool flow usage and deploy solutions.
• Fluent in scripting languages such as TCL, Python, etc., and able to build scalable and efficient flows to support parallel design developments.
• Create dashboards and central reports for project tracking and visualizing QoR/stats.

Basic Qualifications

• BS + 10 years or MS + 7 years in EE/CS.
• 5+ years developing physical design methodology or CAD flows in synthesis, PNR, and sign‑off areas for advanced technology nodes.
• Proficient in programming/scripting languages (Perl, Python, C++).
• Solid understanding of ASIC physical design and methodologies including synthesis, place and route, STA, IR, formal, and physical verification.
• Demonstrated expertise in PD tools such as Innovus, ICC2, Fusion Compiler, STA, and Sign‑Off.
• Proven track record of delivering metric‑driven PPA flow development and support.

Preferred Qualifications

• Expertise in high‑performance, low‑power physical design and implementation techniques with industry‑standard synthesis, PnR, or Sign‑off tools.
• Excellent programming skills in languages like Python, Perl, TCL, Shell, etc., with a strong understanding of algorithms and optimization.
• Knowledge of technology nodes across foundries.
• Experience evaluating multiple vendor solutions and driving tool decisions.
• Knowledge of creating dashboards and status reports for various EDA tool outputs, QoR metrics, and trend analysis (synthesis, PNR, sign‑off, etc.).
• Experience with machine learning.
• Excellent verbal and written communication skills.
• Ability to work in a dynamic environment with changing needs and requirements.
• Ability to provide mentorship, guidance to junior engineers, and be an effective team player.
• Meets/exceeds Amazon’s leadership principles requirements for this role.
• Meets/exceeds Amazon’s functional/technical depth and complexity for this role.

Location and Compensation

USA, TX, Austin - 159,200.00 - 215,300.00 USD annually.

The base salary range for this position is listed below. Your Amazon package will include sign‑on payments and restricted stock units (RSUs). Final compensation will be determined based on experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance; optional supplemental life plans, EAP, mental health support, medical advice line, flexible spending accounts, adoption and surrogacy reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Our inclusive culture empowers Amazonians to deliver the best results for our customers.