Senior PCIe Engineer: PHY & Link Analysis

Energy Jobline ZR; San Jose (CA); On-site; USD 163,000 - 253,000; Full time

Benefits offered by this job

PTO 4+ weeks

Medical/Dental/Vision/401k

Fertility/adoption stipend

Onsite gym

Flexible benefits

Job summary

Samsung Semiconductor is seeking a dynamic engineer to develop and support enterprise and data center SSD products. You will own the PCIe protocol stack from PHY through the Data Link and Transport layers, collaborating with hardware teams to bring up and debug complex links.

Required are 8+ years in hardware/firmware with C/C++ for embedded systems, LTSSM experience, and proficiency with PCIe protocol analyzers and debuggers. Up to 25% travel and on-site work at customer labs are expected.

Qualifications

• BS in Electrical/Computer Engineering or CS; 8+ years experience required.
• MS in Electrical/Computer Engineering or CS; 5+ years experience will be considered.

Responsibilities

• Protocol Stack Analysis from PHY to Transport Layer.
• Lead Link Bring-up, training, and enumeration sequences.
• Analyze and validate TLP/DLLP handling, flow control, and error handling (AER).
• Debug complex PHY/Link/Transport issues during bring-up and sustainment of NVMe SSDs.
• Support PCI-SIG compliance tests and field tasks at customer sites.
• Travel up to 25% for on-site work and labs.

Skills

PCIe protocol

LTSSM

C/C++ embedded

Protocol analyzers

Education

BS in Electrical/Computer Engineering or CS

MS in Electrical/Computer Engineering or CS

Tools

PCIe protocol analyzers

Logic analyzers

JTAG/ICE debuggers

NVMe/SAS protocols

Job description

Samsung Semiconductor is seeking a dynamic engineer to develop and support enterprise and data center SSD products. You will own the PCIe protocol stack from PHY through the Data Link and Transport layers, collaborating with hardware teams to bring up and debug complex links.

Required are 8+ years in hardware/firmware with C/C++ for embedded systems, LTSSM experience, and proficiency with PCIe protocol analyzers and debuggers. Up to 25% travel and on-site work at customer labs are expected.