Senior Out-of-Order CPU Architect

Intel Corporation; Austin (TX); On-site; USD 190,610 - 361,480; Full time

Benefits offered by this job

Health benefits

Retirement plans

Stock bonuses

Vacation benefits

Job summary

Intel Corporation is seeking an experienced CPU Architect in Austin, Texas. This role will drive CPU architecture specifications and work on innovative designs for high-performance computing. With 15+ years of relevant experience required, you'll affect cross-functional collaboration and define technological targets.

The role includes developing architecture specifications and creating test plans, vital for enabling cutting-edge technology solutions that meet market demands. Competitive compensation and benefits are offered.

Qualifications

• 15+ years in CPU design or architecture, preferably in high performance/high frequency.
• 10+ years in out‑of‑order CPU pipeline operations.
• 5+ years writing RTL with power convergence experience.
• 2+ years building advanced schedulers.

Responsibilities

• Develop end-to-end CPU architecture specifications.
• Define performance and power targets aligning with market needs.
• Invent and specify new architectural features for future CPU usage.
• Create test plans and analyze results with statistical techniques.
• Collaborate on roadmaps and drive new microarchitecture definitions.

Skills

Analytical skills

Problem-solving skills

Collaboration skills

Job description

Job Overview

As a CPU Architect, you will be at the forefront of Intel's innovation, shaping the future of CPU designs for high‑performance computing and low‑power products. This role is integral to Intel's mission to deliver cutting‑edge solutions that power the world's technology, from advanced data centers to everyday consumer devices. You will play a pivotal role in driving end‑to‑end CPU architecture specifications, ensuring optimal performance, power efficiency, scalability, and interoperability across hardware and software. Through creative problem‑solving and collaboration, you will influence cross‑functional roadmaps, define technology targets, and deliver revolutionary CPU architectures that meet diverse market requirements.

Key Responsibilities

• Develop and drive end‑to‑end CPU architecture specifications based on hardware features, requirements, and lifecycle needs.
• Define CPU targets for performance, power, frequency, area, and feature content to align with market requirements.
• Explore new approaches and devise novel architectures that deliver optimized CPUs for multiple segments, from high‑performance computing to extreme low‑power applications.
• Invent, conceptualize, and specify architectural and microarchitecture features that address future CPU usage and segment needs.
• Define and document new instructions to support innovative use cases and improve existing ones, enhancing the instruction set architecture (ISA).
• Develop and execute test plans and infrastructure for new architectures/features, simulate functional models, and analyze test results using advanced statistical techniques.
• Propose experimental changes and design alternatives to meet constraints for performance, power, area, and timing.
• When required, directly implement microarchitectural specifications in SystemVerilog. If designers require aid in converging timing and/or power constraints, you are expected to resolve issues quickly.
• Review and influence cross‑functional roadmaps and collaborate with architects, design, verification, and validation engineers during project execution.
• Drive definition of new microarchitectures and identify mitigations for issues during feature implementation to improve CPU designs.

Minimum Qualifications

• 15+ consecutive years of experience within high performance/high frequency ARM or x86 CPU organizations working in either the design or architectural domain.
• 10+ years of experience working within the out‑of‑order sections of the CPU pipeline, including wide instruction rename and allocation, uop/instruction schedulers, and execution units.
• 5+ years writing RTL and owning it through timing and power convergence across multiple generations of a CPU line.
• 2+ years of experience building deep, high‑frequency advanced integer and/or floating‑point/vector schedulers.

Preferred Qualifications

• Strong analytical and problem‑solving skills demonstrated through leadership roles or team management.
• Effective collaboration skills to work across teams and influence cross‑functional roadmaps.
• Passion for driving innovation and contributing to Intel's mission of delivering world‑class technology solutions.

Job Type, Shift and Locations

Job Type: Experienced Hire Shift: Shift 1 (United States of America)
Primary Location: US, Texas, Austin
Additional Locations: Business group: Silicon and Platform Engineering Group (SPE)

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Annual Salary Range for jobs which could be performed in the US: $190,610.00 - $361,480.00 USD. The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.