Senior Optical Engine Package Layout Engineer

CspeedIO, Inc.; Palo Alto (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Cspeed IO is a Palo Alto-based startup developing next-generation optical semiconductor solutions for AI infrastructure. You will own the physical design of our optical engine packages—from floorplan through tape-out—and influence architecture across design, SI/PI, thermal, and supply-chain teams.

This hands-on role requires collaboration with PIC/EIC teams and external vendors to define floorplans, manage DFM/DFA, and drive reliable, high-speed layouts through volume production.

Qualifications

• Required: BS/MS in Electrical Engineering or equivalent practical background.
• 6+ years in IC package physical design, with at least one product from concept to tape-out.
• Expert-level proficiency in package layout tools and multi-die packaging know-how.
• Fluency in English and experience working across time zones.

Responsibilities

• Deliver RDL/UBM and package substrates from floorplan through tape-out.
• Define bump maps, ball maps, and escape routing for multi-die assemblies.
• Design to 200G/lane-class electrical requirements with proper power delivery.
• Co-design floorplans and stack-ups reconciling electrical, optical, thermal, and mechanical constraints.
• Collaborate with wafer fabs, substrate suppliers, and OSATs; drive DFM/DFA closure.
• Run physical verification (DRC/LVS) and manage netlists across revisions.

Skills

IC package design

Multi-die packaging experience

English communication

Education

Bachelor's or Master's in Electrical Engineering

Tools

Cadence Allegro Package Designer

APD+

SiP

Siemens Xpedition Package Designer

Synopsys IC Package

Cadence Integrity 3D-IC

Cadence Sigrity/PowerSI

GDS-based tools (Virtuoso, KLayout)

Python scripting

Job description

Cspeed IO is a Palo Alto-based startup developing next-generation optical semiconductor solutions for AI infrastructure. You will own the physical design of our optical engine packages—from floorplan through tape-out—and influence architecture across design, SI/PI, thermal, and supply-chain teams.

This hands-on role requires collaboration with PIC/EIC teams and external vendors to define floorplans, manage DFM/DFA, and drive reliable, high-speed layouts through volume production.