Senior Modem PHY IP Architect for Terawave ASIC

Blue Origin

Cupertino (CA)

On-site

USD 180,000 - 260,000

Full time

9 days ago
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Job summary

Blue Origin seeks a Principal Modem PHY IP Design Engineer to lead modem PHY architecture, modeling, and implementation for the Terawave program. You will collaborate with systems, RTL, RF, verification, FPGA, firmware, and validation teams to deliver high-performance wireless ASIC solutions.

The role emphasizes strong digital communications theory, hardware-oriented design, and cross-functional teamwork in a fast-paced space tech environment. Location is Cupertino, CA with on-site work expected.

Qualifications

  • Bachelor's degree in a technical field with 10+ years in wireless/PHY design.
  • Strong background in modem implementation and digital comms theory.
  • Experience translating algorithms to hardware-oriented architectures.

Responsibilities

  • Design and develop modem PHY IP for Terawave ASIC and prototyping platforms.
  • Develop PHY algorithms and hardware architecture for modulation, sync, channel estimation, and MIMO.
  • Translate requirements into implementation-ready PHY block specs.
  • Create models (floating/fixed-point) and perform performance analyses across throughput and power.

Skills

Modem PHY design
Digital communications theory
ASIC/FPGA development
MIMO/beamforming
MATLAB
Python
C/C++
System-level debugging
Cross-functional collaboration
Quantitative problem solving

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Applied Mathematics, Physics
Master's degree in Electrical Engineering or related field
PhD in Electrical Engineering or related field

Tools

MATLAB
Python
C/C++
RTL design
FPGA prototyping
Lab characterization

Job description

Blue Origin seeks a Principal Modem PHY IP Design Engineer to lead modem PHY architecture, modeling, and implementation for the Terawave program. You will collaborate with systems, RTL, RF, verification, FPGA, firmware, and validation teams to deliver high-performance wireless ASIC solutions.

The role emphasizes strong digital communications theory, hardware-oriented design, and cross-functional teamwork in a fast-paced space tech environment. Location is Cupertino, CA with on-site work expected.

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