Senior Mixed-Signal Verification Engineer

Intel

Hillsboro (OR)

Hybrid

USD 122,000 - 200,000

Full time

21 hours ago
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Benefits offered by this job

Stock bonuses
Health benefits
Retirement plan
Vacation

Job summary

Intel is seeking an Experienced Verification Engineer in Hillsboro, OR to perform functional verification of mixed-signal logic and develop robust verification environments. You will collaborate with architects, RTL, and physical-design teams to meet functional, performance, and power goals.

The role requires strong digital logic skills and experience with VHDL/Verilog/SystemVerilog, OVM/UVM testbenches, and debugging complex designs. A hybrid work model is available in the US.

Qualifications

  • Bachelor's degree with 3+ years of relevant experience or Master’s degree with 2+ years of relevant experience.
  • Experience with digital and analog verification environments and schemes.
  • Proficiency in VHDL/Verilog/SystemVerilog and testbench development in OVM/UVM.

Responsibilities

  • Performs functional verification of mixed-signal logic components and ensures design meets specifications.
  • Develops IP verification plans, test benches, and the verification environment for coverage and compliance.
  • Executes verification plans, runs system simulations, analyzes power and timing, and debugs issues.

Skills

Digital logic
VHDL/Verilog/SystemVerilog
Testbench development (OVM/UVM)
Debugging skills
Analog debug skills

Education

Bachelor's Degree in Electrical Engineering/Computer Engineering/Computer Science
Master's Degree in Electrical Engineering/Computer Engineering/Computer Science

Job description

Intel is seeking an Experienced Verification Engineer in Hillsboro, OR to perform functional verification of mixed-signal logic and develop robust verification environments. You will collaborate with architects, RTL, and physical-design teams to meet functional, performance, and power goals.

The role requires strong digital logic skills and experience with VHDL/Verilog/SystemVerilog, OVM/UVM testbenches, and debugging complex designs. A hybrid work model is available in the US.

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