Senior Mixed-Signal IC Design Engineer, High-Speed IO

NVIDIA Corporation; Santa Clara (CA); On-site; USD 168,000 - 311,000; Full time

Job summary

NVIDIA Corporation in Santa Clara is seeking a Senior Mixed Signal Design Engineer to join the Mixed Signal design team building next generation NVLINK. The role offers impact on products from graphics to AI and autonomous driving.

You will design high-speed interfaces, transceivers, PLLs; lead layout teams; mentor designers; bring designs to silicon characterization and productize. Collaboration with multi-functional teams and hands-on experience across concept to silicon, with deep submicron

Qualifications

• MS in Electrical Engineering (or equivalent); PhD preferred
• 4+ years of CMOS analog/mixed-signal design experience
• Experience with Data Converters, Tx/Rx, CDR and PLL for high-speed IO interfaces
• Proven mentoring and leadership of designers
• Deep submicron CMOS process knowledge and lab bring-up experience
• Experience with silicon bring-up, debugging and lab instrumentation

Responsibilities

• Design and implement high-speed interface circuits
• Create projects including high speed transceivers and high frequency PLLs
• Design, simulate, and verify mixed-signal circuits
• Lead mask designers and mentor floorplan/layout design
• Support lab characterization of silicon and productize designs
• Collaborate with multi-functional teams

Skills

CMOS analog/mixed-signal design

High-speed interfaces

Verilog

Matlab

Nanotime

Education

MS in Electrical Engineering

Tools

Cadence tools

Verilog

Matlab

Nanotime

Job description

NVIDIA Corporation in Santa Clara is seeking a Senior Mixed Signal Design Engineer to join the Mixed Signal design team building next generation NVLINK. The role offers impact on products from graphics to AI and autonomous driving.

You will design high-speed interfaces, transceivers, PLLs; lead layout teams; mentor designers; bring designs to silicon characterization and productize. Collaboration with multi-functional teams and hands-on experience across concept to silicon, with deep submicron