Mask Design Engineer – Hardware

NVIDIA; Oregon; On-site; USD 108,000 - 184,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA seeks a Senior Mask Design Engineer in Oregon to join a dynamic team focused on advanced packaging solutions. You will collaborate with PTL and I/O engineers, performing physical layout for silicon interposers using Cadence tools to meet tight schedules.

The role requires a BS in Electrical Engineering and 3+ years of mask and layout design experience, with expertise in Cadence Virtuoso and LVS/DRC workflows.

Qualifications

• B.S. in Electrical Engineering or equivalent.
• 3+ years of mask and layout design experience.
• Deep understanding of submicron CMOS layout concepts.
• Proficiency with Cadence tools, especially Virtuoso.
• Experience with DRC/LVS and custom deck customization.

Responsibilities

• Collaborate with PTL and I/O signal integrity and tech engineers to deliver package solutions on tight schedules.
• Perform physical layout for silicon interposer using Cadence tools.
• Conduct design feasibility studies for package size, cost, and system performance.
• Study layout floorplans and perform custom layout verification against rules and netlists.
• Propose layout trade-offs to PTL for resolution and implementation.

Skills

Mask design

Layout design

Cadence Virtuoso

Perl/Python scripting

DRC/LVS workflows

APD packaging tools

Education

B.S. Electrical Engineering

Tools

Cadence tools

Virtuoso

Calibre

ICV/Thunder

Job description

NVIDIA’s GPUs and SOCs are the world leaders in power, performance, and efficiency. We are continually innovating to deliver new and creative, unusual solutions to extraordinary problems in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Mask Design Engineer who is committed to making a difference in the world through their contributions!

What You'll Be Doing

• You'll collaborate cross functionally with package technical lead (PTL) and I/O signal integrity and technology engineers to deliver solution for product packages in tight schedule.
• Performing physical layout for silicon interposer using Cadence tools.
• Conduct design feasibility studies to evaluate the package design goals for size, cost, and system performance.
• Take part in studying layout floorplan and perform custom layout and verification against design rules and netlists.
• Propose layout design trade-offs to the PTL for resolution and implementation.

What We Need To See

• Hold a B.S. Electrical Engineering or equivalent experience
• 3+ years proven experience in Mask and Layout Design.
• Deep understanding of layout concepts in submicron CMOS technologies.
• You are an authority with Cadence layout tools - particularly Virtuoso.
• Knowledge of Integrity auto-routing is a plus.
• Experience running and debugging with verification tools such as Calibre, ICV, Thunder, etc.
• Proficient in scripting languages like Perl, Python, Skill, etc.
• Should have knowledge of DRC and LVS checking flows, ability to customize decks.
• Knowledge of APD package layout tool is a plus.
• Good understanding of packaging technology is useful.
• You can work optimally in a team, good interpersonal skills, passion and positive energy.

NVIDIA is widely considered to be one of the technology world's most desirable employers! We have some of the most forward-thinking and dedicated people in the world working for us.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 108,000 USD - 184,000 USD.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until October 17, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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