Senior Manager, High-Speed Hardware & Signal Integrity

TE Connectivity Ltd.; Troy (MI); In loco; USD 180.000 - 240.000; Tempo pieno

Vantaggi offerti da questo lavoro

Health insurance

401(k)

Disability insurance

Life insurance

Employee stock purchase plan

Paid time off

Voluntary benefits

Descrizione del lavoro

TE Connectivity Ltd. is seeking an experienced engineering leader to manage the integrated Hardware and Signal Integrity organization for high-speed external cable assemblies.

You will own the full lifecycle from architecture to production, driving DAC, ACC, and AEC architectures across OSFP, QSFP-DD, QSFP, and related form factors. You will lead global teams, advance SerDes and channel modeling, and optimize link margins, power, EMI/EMC, and thermal performance for Ethernet and PCIe

Competenze

• 12+ years of relevant engineering experience, including 5+ years in technical or people leadership.
• Strong expertise in high-speed hardware design, signal and power integrity, PCB design, channel modeling, S-parameters, SerDes, and laboratory characterization.
• Hands-on understanding of DAC, redriver-based ACC, and retimer-based AEC product architectures.

Mansioni

• Lead global Hardware, PCB Design, and Signal Integrity engineering teams across passive and active external cable products.
• Own electrical architecture, hardware design, SI/PI analysis, PCB implementation, and design verification.
• Drive ACC development using linear redriver technology and AEC development using retimer technology, including performance and interoperability considerations.

Conoscenze

High-speed hardware design

Signal and power integrity

PCB design

Channel modeling

S-parameters

SerDes

Laboratory characterization

Formazione

Electrical Engineering degree

Descrizione del lavoro

TE Connectivity Ltd. is seeking an experienced engineering leader to manage the integrated Hardware and Signal Integrity organization for high-speed external cable assemblies.

You will own the full lifecycle from architecture to production, driving DAC, ACC, and AEC architectures across OSFP, QSFP-DD, QSFP, and related form factors. You will lead global teams, advance SerDes and channel modeling, and optimize link margins, power, EMI/EMC, and thermal performance for Ethernet and PCIe