Senior Lead Analog Design Engineer – Mixed-Signal IP

Global Foundries; Richardson (TX); On-site; USD 126,000 - 218,000; Full time

Job summary

GlobalFoundries in Richardson, TX seeks a Sr. Staff Engineer, Analog Design to lead the development of high‑performance analog and mixed‑signal IP, defining architecture, owning circuit design, and validating silicon with cross‑functional teams across layout, verification, and SoC integration.

The ideal candidate has deep CMOS analog expertise, strong technical leadership, and mentoring skills, with experience in transistor‑level design, tolerance analysis, and AMS simulations, and a track

Qualifications

• Bachelor’s or master’s degree in electrical or computer engineering.
• 10+ years of analog mixed-signal design experience.
• Concept-to-silicon delivery of complex analog IP blocks.
• Deep CMOS analog design fundamentals, noise and variation.
• Experience with power, performance and area constraints.
• Experience with industry-standard EDA tools.
• Ability to document requirements and architecture clearly.
• Leadership and cross-functional collaboration.

Responsibilities

• Drive design and development of complex analog and mixed-signal IP blocks.
• Own architecture and transistor-level schematic design with verification.
• Perform corner, Monte Carlo, and reliability analyses for robust silicon.
• Collaborate with layout, AMS verification, and SoC integration teams.
• Lead design reviews and drive silicon validation activities.

Skills

Analog/mixed-signal design

Transistor-level design

CMOS design fundamentals

Scripting: Python & PERL

AMS simulations

Debugging & problem solving

Leadership & mentoring

Layout collaboration

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering

Tools

Cadence

Synopsys

Ansys

Virtuoso

Job description

GlobalFoundries in Richardson, TX seeks a Sr. Staff Engineer, Analog Design to lead the development of high‑performance analog and mixed‑signal IP, defining architecture, owning circuit design, and validating silicon with cross‑functional teams across layout, verification, and SoC integration.

The ideal candidate has deep CMOS analog expertise, strong technical leadership, and mentoring skills, with experience in transistor‑level design, tolerance analysis, and AMS simulations, and a track