Senior IP Project Engineer

NXP Semiconductors; Austin (TX); On-site; USD 140,000 - 200,000; Full time

Job summary

NXP's ACE Digital IP team in Austin seeks a Senior IP Project Engineer to drive end‑to‑end IP and subsystem development from architecture through release, delivering robust, low‑power, automotive‑grade solutions.

You will coordinate across architecture, design, verification, validation and software teams, manage schedules and risks, and ensure on‑time delivery with clear milestones and quality gates for multiple business lines.

Qualifications

• BSEE required; MSEE preferred.
• Experience with IP development processes and methodology.
• Experience with RTL design flow, timing, DFT, and interfaces.
• Strong planning, scheduling, risk management, and cross‑functional leadership.

Responsibilities

• Drive end‑to‑end IP and subsystem milestones from architecture through release.
• Coordinate across architecture, design, verification, validation, software, and SoC teams.
• Identify risks early, drive resolution, and escalate critical issues.
• Lead technical reviews and checkpoints with clear status and actions.
• Align specifications, interfaces, release content, and hand‑off requirements.
• Manage priorities, trade‑offs, and dependencies within IP scope.
• Support release readiness and milestone tracking with data.

Skills

IP development process

Technical leadership

RTL design flow

Cross-functional collaboration

Education

BSEE

MSEE preferred

Tools

Microsoft Project

Jira

Confluence

Power BI

Excel

Job description

Overview

Senior IP Project Engineer – Primary Location: Austin, Texas. We are part of ACE (AI & Chip Engineering), a central design organization within NXP, developing products for multiple business lines in Automotive, Internet of Things (IoT), Networking, and Radio Frequency products, with expertise in hardware engineering, including architecture, IP, and full SoC design. The ACE Digital IP team produces design solutions covering the very wide range of SoCs required by the business lines. The team is challenged to produce industry‑leading solutions covering very cost‑sensitive, low‑power devices to highly integrated, high‑performance, multi‑cohort devices compliant with the latest automotive and industrial safety and security standards.

Responsibilities

• Work closely with architects, designers, verification engineers, and integration teams to drive execution and delivery of complex IP and subsystem development.
• Own end‑to‑end execution and delivery of IP and subsystem milestones from architecture through release.
• Define development phases, schedules, milestones, dependencies, and quality expectations with architects and engineering leads.
• Coordinate execution across architecture, design, verification, validation, software, and SoC integration teams.
• Identify risks early, drive resolution, and elevate critical issues that threaten execution, quality, or release commitments.
• Lead technical reviews and execution checkpoints with clear status, actions, and follow‑through.
• Drive alignment on specifications, interfaces, release content, and hand‑off requirements.
• Drive priority and trade‑off discussions within IP scope.
• Resolve interface issues, integration dependencies, and execution trade‑offs with internal and external stakeholders.
• Support release readiness, sign‑off reviews, and integration milestones by driving issues to closure.
• Improve execution visibility through data collection, milestone tracking, risk registers, and engineering metrics.

Qualifications

• BSEE required; MSEE preferred with 7+ years of industry related experience.
• Good understanding of IP development process and methodology with technical depth and project execution leadership.
• Experience in protocols such as AHB/AMBA, memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers.
• Experience driving execution across multidisciplinary teams, with ownership of plans, schedules, dependencies, risks, and tracking.
• Strong planning skills and hands‑on use of Microsoft Project, Jira, Confluence, Power BI, and Excel for scheduling, tracking, risk management, and data collection.
• Good understanding of semiconductor development lifecycle, design and verification methods, and integration dependencies.
• Experience in all aspects of RTL design flow from specification/microarchitecture definition to design and verification, timing analysis, DFT and implementation.
• Good understanding of chip assembly, IP integration, RTL sign‑off tools and CDC/RDC/Lint/Synthesis.
• Able to work effectively with global teams; self‑motivated to solve problems and manage deliverables.
• Excellent interpersonal and communication skills.
• Excellent leadership and negotiation skills.

EEO Statement

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.