Senior IC Packaging Design & Layout Engineer

The Charles Stark Draper Laboratory, Inc.; Cambridge (MA); On-site; USD 82,300 - 220,000; Full time

Job summary

The Charles Stark Draper Laboratory, Inc. is seeking an IC Packaging Design & Layout Engineer in Cambridge, MA.

You will own end-to-end packaging solutions that meet performance, power, size, and reliability targets for Draper’s next-generation hardware platforms. Responsibilities include leading advanced package concepts, detailed die-to-die routing, SI/PI strategies, and cross-functional collaboration with silicon design, thermal, and manufacturing teams.

Qualifications

• Bachelor's degree in electrical engineering or related field.
• Advanced degree preferred.
• 5–10 years of experience in electrical engineering or related field.

Responsibilities

• Lead concept development for advanced packages (e.g., fan out wafer level, 2.5D/3D interposer, system in package).
• Produce detailed layout for substrates, interposers, and die-to-die routing using Siemens Xpedition.
• Own package-level SI/PI strategy, including high-speed interfaces, PDN design, and decoupling strategy.
• Perform SPICE, EM, and S‑parameter simulations to validate SI, PDN, and crosstalk.
• Collaborate with mechanical, silicon, RF, and board design engineers to optimize layouts.
• Author package build documentation, specifications, and test plans.

Skills

High density packaging layout

Signal integrity best practices

SI/PI analysis tools

Education

Bachelor's degree in electrical engineering

Advanced degree preferred

Tools

Siemens Xpedition

Ansys SIwave

HFSS

Hyperlynx

Job description

The Charles Stark Draper Laboratory, Inc. is seeking an IC Packaging Design & Layout Engineer in Cambridge, MA.

You will own end-to-end packaging solutions that meet performance, power, size, and reliability targets for Draper’s next-generation hardware platforms. Responsibilities include leading advanced package concepts, detailed die-to-die routing, SI/PI strategies, and cross-functional collaboration with silicon design, thermal, and manufacturing teams.