Senior IC Layout Engineer: High-Speed, Low-Noise ADC/DAC (Optical)

Technical-Link N. America; Austin (TX); On-site; USD 120,000 - 160,000; Full time

Job summary

Technical-Link N. America seeks an accomplished layout engineer for a well-funded startup environment in Austin, TX. You will develop high-end ADC/DAC devices in advanced processes for optical communication and lead layout activities with Cadence tools.

Qualifications focus on 10+ years in sub-micro process (2n to 16n, TSMC), expertise in high-speed, low-noise layout design, tape-out procedures, and strong teamwork. Experience with FinFET/GAA technologies is a plus.

Qualifications

• 10+ years in sub-micro process (2n up to 16n) at or with TSMC
• Expertise in high-speed low-noise layout design
• Expertise in Cadence Layout tools
• TSMC FINFET and/or Gate All Around technologies design
• Good understanding of schematic flow
• Teamwork
• Experience in tape-out procedures

Skills

High-speed layout design

Low-noise layout design

Team leadership

Tape-out procedures

Tools

Cadence Layout tools

Mentor tools

Job description

Technical-Link N. America seeks an accomplished layout engineer for a well-funded startup environment in Austin, TX. You will develop high-end ADC/DAC devices in advanced processes for optical communication and lead layout activities with Cadence tools.

Qualifications focus on 10+ years in sub-micro process (2n to 16n, TSMC), expertise in high-speed, low-noise layout design, tape-out procedures, and strong teamwork. Experience with FinFET/GAA technologies is a plus.