Senior IC Design Engineer - High-Speed Optical PHY Equity

Broadcom; Irvine (CA); On-site; USD 140,000 - 200,000; Full time

Benefits offered by this job

Equity grant

Discretionary annual bonus

401(k) matching

Health insurance

Job summary

Broadcom in Irvine, CA is seeking a senior ASIC design engineer to architect block level designs for high-speed optical communication transceivers. You will translate marketing requirements into detailed designs, manage timing, and oversee RTL coding, synthesis, and validation.

You should have a strong background in ARM subsystems, high-speed digital circuits, RTL languages (Verilog/VHDL), and scripting (Python/Unix). Extensive collaboration across remote teams is expected.

Qualifications

• B.S. in EE or CE; minimum 8 years related experience.
• M.S./Ph.D. in EE/CE with 6+ years preferred.
• Strong knowledge of ARM subsystems.
• Expertise in high-speed digital circuit design and Ethernet/OTN familiarity.
• Experience with FEC and DSP concepts is a plus.
• Hands-on lab debugging and design-for-test experience.
• Proficiency in RTL simulation, synthesis and timing closure.

Responsibilities

• Architect block-level design from marketing/system requirements.
• Prepare design documents and timing constraints.
• RTL coding, lint, CDC, synthesis, and RTL/gate-level simulations.
• Perform design tradeoffs for leakage, power and area.
• Silicon bring-up, ATE program support, and validation.
• Develop verification and test plans for design validation.

Skills

ARM subsystem

high speed digital design

RTL design

RTL simulation

Scripting/Python/Unix

Verilog

VHDL

C

Synthesis/Timing

Power/TPD design

Education

B.S in EE or Computer Engineering

M.S or Ph.D in EE/CE

Tools

Verilog

VHDL

Unix/Perl/Python

Job description

Broadcom in Irvine, CA is seeking a senior ASIC design engineer to architect block level designs for high-speed optical communication transceivers. You will translate marketing requirements into detailed designs, manage timing, and oversee RTL coding, synthesis, and validation.

You should have a strong background in ARM subsystems, high-speed digital circuits, RTL languages (Verilog/VHDL), and scripting (Python/Unix). Extensive collaboration across remote teams is expected.