Senior High-Speed PCB Layout Engineer

UST; Mountain View (CA); On-site; USD 56,000 - 84,000; Full time

Benefits offered by this job

401(k) with employer matching

Medical, dental, and vision insurance

Paid time off

Paid holidays

Job summary

UST is seeking a Layout Engineer to contribute to high-speed PCB design and layout for advanced GPU, CPU, and server platforms. You will define ball-out, footprints, routing strategies, and stack-ups while ensuring constraints are met.

Collaborate with SI/PI, Mechanical, Thermal, Packaging, and Manufacturing teams to optimize performance and manufacturability, perform PCB verification, and generate fabrication outputs such as ODB++, Gerbers, and docs.

Qualifications

• Bachelor's Degree in Electrical Engineering and 5+ years of related experience; or Master's Degree with 3+ years of related experience.
• Proficient in schematic design using Altium or equivalent (Altium preferred).
• Experience with high-speed interfaces and design automation initiatives.

Responsibilities

• Define ASIC ball-out, component footprint and placement, routing strategy, stack-ups, and design constraints.
• Develop and implement design rules for high-speed interfaces including PCIe, memory, SERDES, and power delivery networks.
• Collaborate with Board Design, SI/PI, Mechanical, Thermal, Packaging, and Manufacturing teams to optimize design performance and manufacturability.
• Execute PCB verification and design rule checks to ensure design quality and release readiness.
• Generate and review manufacturing outputs including ODB++, Gerbers, and fabrication documentation.

Skills

PCB design

Altium

High-speed routing

HDI technologies

BGA designs

Impedance control

Power delivery

Schematic design

Electrical engineering basics

Education

Bachelor's Degree in Electrical Engineering

Tools

Altium Designer

Job description

UST is seeking a Layout Engineer to contribute to high-speed PCB design and layout for advanced GPU, CPU, and server platforms. You will define ball-out, footprints, routing strategies, and stack-ups while ensuring constraints are met.

Collaborate with SI/PI, Mechanical, Thermal, Packaging, and Manufacturing teams to optimize performance and manufacturability, perform PCB verification, and generate fabrication outputs such as ODB++, Gerbers, and docs.