Senior High-Speed Analog/Mixed-Signal IC Designer

Phizenix Inc.; Santa Clara, Irvine (CA, CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Phizenix Inc. seeks a Senior Analog & Mixed-Signal IC Designer to join a world-class semiconductor team. Deep expertise in high-speed analog circuit design, wireline SerDes front-ends, RFIC front-ends, and precision data converters is required. Silicon delivery in advanced FinFET/SOI processes is expected.

You will design and verify ADCs/DACs/PLLs, develop TIAs, drive pre-silicon sims and post-silicon bring-up, and mentor junior engineers within a cross-functional group.

Qualifications

• PhD in EE with 6+ years in analog/mixed-signal IC design.
• MS in EE with 8+ years in analog/mixed-signal IC design.
• Experience in high-speed analog and RF front-end design.

Responsibilities

• Design and verify high-speed analog/mixed-signal circuits (ADCs, DACs, PLLs, TIAs).
• Architect wireline SerDes front-ends and multi-GHz analog signal chains from concept to tape-out.
• Develop transistor-level schematics and layouts in FinFET (7–16 nm) or SOI.
• Drive pre-silicon simulation and post-silicon bring-up; analyze silicon data and iterate on design.
• Partner with digital, CAD, and systems teams on mixed-signal partitioning and specs.
• Produce detailed design documentation and present progress to stakeholders.
• Mentor junior designers and contribute to best-practice development.

Skills

Analog design

High-speed circuits

TIAs

Clocking systems

LNA/Mixer

ADC/DAC design

Education

PhD in EE

MS in EE

Tools

Cadence Virtuoso

Spectre

Ultrasim

Job description

Phizenix Inc. seeks a Senior Analog & Mixed-Signal IC Designer to join a world-class semiconductor team. Deep expertise in high-speed analog circuit design, wireline SerDes front-ends, RFIC front-ends, and precision data converters is required. Silicon delivery in advanced FinFET/SOI processes is expected.

You will design and verify ADCs/DACs/PLLs, develop TIAs, drive pre-silicon sims and post-silicon bring-up, and mentor junior engineers within a cross-functional group.