Senior HBM SoC RTL Design Engineer

Micron Technology; Folsom (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

Micron Technology is looking for a SoC Design Engineer in Folsom, California, to contribute to next-generation HBM SoC logic die development. The role involves designing and implementing RTL for SoC-level blocks, collaborating with multi-functional teams, and participating in integration activities.

Candidates should have at least 10 years of experience in electrical or computer engineering and be proficient in SystemVerilog. Ideal candidates will also have experience with EDA tools and scripting.

Qualifications

• Minimum of 10 years of experience in a related field.
• Familiarity with RTL-to-GDS flow, synthesis, static timing analysis.
• Exposure to DFT concepts and debug.

Responsibilities

• Design and implement RTL for SoC-level blocks used in HBM logic die.
• Collaborate with SoC architects on specifications.
• Assist with pre-silicon validation and root-cause analysis.

Skills

SystemVerilog/Verilog

SoC integration methodologies

Programming or scripting (Python, TCL, Perl)

Education

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or related field

Tools

EDA tools (Cadence, Synopsys, Siemens)

Job description

Micron Technology is looking for a SoC Design Engineer in Folsom, California, to contribute to next-generation HBM SoC logic die development. The role involves designing and implementing RTL for SoC-level blocks, collaborating with multi-functional teams, and participating in integration activities.

Candidates should have at least 10 years of experience in electrical or computer engineering and be proficient in SystemVerilog. Ideal candidates will also have experience with EDA tools and scripting.