Senior Hardware/Software Design Engineer (HSDE-3)

Via Logic LLC; Corridor North (MD); On-site; USD 131,300 - 237,350; Full time

Benefits offered by this job

Cash sign-on bonus up to $25,000

Paid time off

401(k) with 6% company match

Flexible schedules

Technical upskilling support

Job summary

Via Logic LLC is looking for a Senior Hardware/Software Design Engineer to develop and test electronic hardware and software components for RF communication. This role requires strong proficiency in FPGA coding and digital signal processing, alongside a bachelor’s degree and significant experience.

The ideal candidate will lead design efforts, implement algorithms in FPGA, and integrate with Linux code bases, all while working in a collaborative and fast-paced environment. Benefits include competitive pay, a sign-on bonus, and various support programs.

Qualifications

• 8 years of relevant experience or equivalent.
• Active TS/SCI with Polygraph security clearance required.

Responsibilities

• Implement DSP and technical components in FPGA.
• Lead technical design efforts and integrate with Linux code.
• Document all engineering efforts.

Skills

FPGA coding

Digital signal processing theory

Coding in C

Coding in C++

Linux OS

Education

Bachelor’s degree

Tools

Vivado

Epiq Solution PDK

Job description

Senior Hardware/Software Design Engineer (CABA)

Our LOE program provides our customer's Signals Analysis organization with the best possible solutions for mission needs. The team focuses on rapid prototyping, new development, and advanced technology research. With a culture of collaboration and a fast‑paced environment, the program is an ideal place to grow your skills and make a real impact.

Job Summary

The position requires an experienced senior HW/SW Design Engineer to design, develop, construct, and test electronic hardware (FPGA) and software processing components for subsystems supporting RF communication and collection systems. Responsibilities include leading technical design efforts, implementing DSP algorithms and associated technical components in FPGA, integrating with existing Linux code bases, bridging FPGA to a software stack, and documenting all efforts.

Responsibilities & Qualifications

• Mission Focus: Implement DSP and associated technical components in FPGA for code base integration.
• Technical Proficiency: Strong experience required in FPGA coding, digital signal processing theory & application, interfacing FPGA code with existing code bases and software; knowledge of signal processing blocks and related DSP components, Linux OS, coding ability in C and C++.
• Qualifications: Bachelor’s degree plus 8 years of relevant experience or equivalent.
• Security Clearance: Active TS/SCI with Polygraph required.
• Desirable Skills: Experience with Vivado required; experience with Epiq Solution PDK preferred.

Qualified candidates are eligible for up to a \$25,000 cash sign‑on bonus or a paid time‑off bonus.

Benefits and Pay

Pay Range: \$131,300.00 – \$237,350.00. Compensation may also reflect responsibilities, education, experience, skills, and market data. Benefits include paid time off, 11 paid holidays, 401(k) with 6% company match and immediate vesting, flexible schedules, discounted stock purchase plans, technical upskilling, education and training support, parental paid leave, health and wellness programs, income protection, paid leave, and retirement options.

EEO Commitment

All qualified applicants will receive consideration for employment without regard to sex, race, ethnicity, age, national origin, citizenship, religion, physical or mental disability, medical condition, genetic information, pregnancy, family structure, marital status, ancestry, domestic partner status, sexual orientation, gender identity or expression, veteran or military status, or any other basis prohibited by law. Leidos will also consider for employment qualified applicants with criminal histories consistent with relevant laws.