Senior Hardware Emulation Engineer – FPGA & AI/ML

Socket.dev; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Job summary

Samsung Semiconductor in San Jose, CA, seeks an experienced hardware emulation engineer to build and optimize large-scale emulation platforms for memory-centric SoCs. You will map designs onto emulation systems, develop co-emulation environments, and enable early firmware bring-up for AI/ML workloads.

Ideal candidates have 5+ years in pre-silicon verification, FPGA prototyping, and hands-on experience with Palladium/ZeBu/Veloci platforms, with strong Verilog/SystemVerilog skills.

Qualifications

• Bachelor's or higher with extensive pre-silicon verification and SoC bring-up.
• 5+ years in FPGA prototyping and large-scale hardware emulation of complex ASIC/SoC designs.
• Experience with emulation platforms and multi-FPGA design partitioning.

Responsibilities

• Build and maintain large-scale hardware emulation and FPGA prototyping platforms.
• Partition multi-million-gate designs onto emulation systems for validation.
• Develop transactors, speed bridges, and co-emulation environments.
• Model memory subsystems, clocks, resets, and high-speed interfaces.
• Enable early firmware bring-up with robust debug infrastructure.
• Run AI/ML workloads pre-silicon to validate performance.
• Debug issues with waveform capture, assertions, and root-cause analysis.
• Automate emulation/prototyping flows using scripting and AI tools.
• Communicate with users and management to deliver on time and budget.

Skills

Verilog/SystemVerilog

FPGA prototyping

Hardware emulation

SCE-MI/co-emulation

Cadence Palladium

Synopsys ZeBu

PCIe/DDR/HBM interfaces

Python scripting

Tcl scripting

clocking and memory modeling

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree (advantage)

PhD (not required)

Tools

Cadence Palladium

Synopsys ZeBu

Siemens Veloce

Synopsys HAPS

Cadence Protium

Job description

Samsung Semiconductor in San Jose, CA, seeks an experienced hardware emulation engineer to build and optimize large-scale emulation platforms for memory-centric SoCs. You will map designs onto emulation systems, develop co-emulation environments, and enable early firmware bring-up for AI/ML workloads.

Ideal candidates have 5+ years in pre-silicon verification, FPGA prototyping, and hands-on experience with Palladium/ZeBu/Veloci platforms, with strong Verilog/SystemVerilog skills.