Senior GPU Design Engineer: RTL & Power

Socket.dev; Austin (TX); On-site; USD 180,000 - 230,000; Full time

Job summary

Apple in Austin, TX is seeking an experienced RTL/SoC design engineer to contribute to GPU power management and SOC interface logic. You will work with Platform Architecture, Software, and Design Verification teams to deliver RTL and specifications while integrating IP across teams.

The role emphasizes timing, power, and area optimization, collaboration across sites, and delivering design collateral to Physical Design teams to meet project milestones.

Qualifications

• BS/MS CE or EE required.
• Experience writing RTL in Verilog and/or SystemVerilog.
• Experience with logic synthesis, timing analysis and floor planning.

Responsibilities

• Deliver RTL design collateral and interfaces to Physical Design teams.
• Assess and integrate IP from other teams.
• Close timing, power, area, and lint for design by optimizing RTL and constraints.
• Drive performance, power, area targets for SOC designs.
• Provide schedules to IP teams and management.
• Collaborate with IP teams across multiple sites.

Skills

RTL design

Verilog/SystemVerilog

Logic optimization

Synthesis

Timing analysis

Floor planning

Power intent descriptions

Clock domain crossings

Education

BS/MS in CE or EE

Job description

Apple in Austin, TX is seeking an experienced RTL/SoC design engineer to contribute to GPU power management and SOC interface logic. You will work with Platform Architecture, Software, and Design Verification teams to deliver RTL and specifications while integrating IP across teams.

The role emphasizes timing, power, and area optimization, collaboration across sites, and delivering design collateral to Physical Design teams to meet project milestones.