Senior FPGA Image Pipeline Engineer

Alcon; Goleta (CA); On-site; USD 131,000 - 169,000; Full time

Job summary

Alcon seeks a Principal FPGA Image Pipeline Engineer to support R&D for surgical instrumentation in Goleta, CA. You will help design next-gen surgical cameras, develop FPGA image pipelines with HLS, and translate C/Matlab algorithms to FPGA fabric, ensuring timing closures and robust testing.

You will work with embedded processors using C, verify with VHDL/Verilog, and interact with customers and suppliers while following Agile practices and version control.

Qualifications

• Bachelor’s Degree or Equivalent years of directly related experience (or high school +13 yrs; Assoc.+9 yrs; M.S.+2 yrs; PhD+0 yrs)
• 5 Years of Relevant Experience
• Relocation and Visa Sponsorship: Yes

Responsibilities

• Developing image processing pipeline on Field-Programmable Gate Array (FPGA) using High Level Synthesis (HLS).
• Translating image processing algorithm from C/Matlab to FPGA fabric in HLS.
• Continuously improving algorithm in C/Matlab and HLS to meet requirement.
• Designing FPGA logic using VHDL and Verilog, writing testbenches for functional simulation. Closing timing on FPGA designs.
• Interfacing FPGA to external hardware peripherals, including high resolution image sensors, temperature sensor, flash memories, etc.
• Programming embedded processors using C language,
• Testing embedded system through UART/RS-232, J-tag debugger, LEDs, oscilloscope, logic analyzer, etc.
• Developing firmware following Agile Design Methodology. Using version control to commit and push firmware code. Performing code review through pull request. Writing detailed design documentation.
• Creating host computer test tool or script using C/C++ or Python to test embedded systems.
• Interact with outside customers, suppliers, and functional peer groups. Communicating to vendors’ field application engineers (FAE) for technical support.

Skills

FPGA design

HLS

C/C++

Python

VHDL/Verilog

Image processing

Debugging hardware

Telemetry/communication interfaces

Education

Bachelor’s Degree or Equivalent years of directly related experience (or high school +13 yrs; Assoc.+9 yrs; M.S.+2 yrs; PhD+0 yrs)

Tools

Xilinx ISE/Vivado

Intel Quartus

ModelSim

Questa

Job description

Alcon seeks a Principal FPGA Image Pipeline Engineer to support R&D for surgical instrumentation in Goleta, CA. You will help design next-gen surgical cameras, develop FPGA image pipelines with HLS, and translate C/Matlab algorithms to FPGA fabric, ensuring timing closures and robust testing.

You will work with embedded processors using C, verify with VHDL/Verilog, and interact with customers and suppliers while following Agile practices and version control.