Senior FPGA Engineer, LEO Payload FPGA, Amazon Leo Hardware Development

Amazon; Redmond (WA); On-site; USD 159,200 - 215,300; Full time

Job summary

Amazon Kuiper Manufacturing Enterprises LLC is seeking an experienced FPGA Design Engineer to create and release FPGA-based solutions for the LEO satellite system. You will own FPGA bitstreams, collaborate with systems teams, and drive networks function implementations on latest FPGA platforms.

The role requires strong Verilog/SystemVerilog skills, RTL design expertise, and experience with Versal ACAP and IGLOO2.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 7+ years of FPGA design experience.
• Experience with AMD Xilinx Versal ACAP FPGA architecture and development tools.
• Demonstrated expertise with Microchip IGLOO2 FPGA platform.
• Strong proficiency in Verilog HDL for RTL design and verification.
• Experience with FPGA design tools (Vivado, Libero SoC, or equivalent).
• Solid understanding of digital design principles, timing analysis, and clock domain crossing.
• Experience with simulation tools (ModelSim, VCS, or similar).
• Strong debugging and problem-solving skills.
• HDL Languages: Verilog (required), SystemVerilog (preferred).
• FPGA Platforms: Versal ACAP, IGLOO2.
• Design Tools: Xilinx Vivado, Microchip Libero SoC.
• Simulation: ModelSim, Vivado Simulator, or equivalent.
• Scripting: Python, TCL, or Perl for design automation.
• Protocols: Understanding of industry-standard communication protocols.

Responsibilities

• Design, develop, and implement complex FPGA architectures using Verilog HDL.
• Lead FPGA design efforts for Versal ACAP and IGLOO2 platforms from concept through production.
• Develop and optimize RTL code for high-performance, resource-efficient designs.
• Perform timing analysis, synthesis, place and route, and design verification.
• Create comprehensive test benches and simulation environments.
• Collaborate with cross-functional teams including hardware engineers, software developers, and system architects.
• Debug and troubleshoot FPGA designs at both simulation and hardware levels.
• Develop technical documentation including design specifications, test plans, and user guides.
• Support hardware integration, manufacturing, and production deployment activities.

Skills

Verilog HDL

SystemVerilog

RTL design

Debugging

Design verification

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Vivado

Libero SoC

ModelSim

VCS

Job description

Description

LEO is Amazon’s low Earth orbit satellite broadband network. Its mission is to deliver fast, reliable internet to customers and communities around the world, and we’ve designed the system with the capacity, flexibility, and performance to serve a wide range of customers, from individual households to schools, hospitals, businesses, government agencies, and other organizations operating in locations without reliable connectivity.

The Role

Create FPGA solutions to support LEO's satellite communication system. This is a unique opportunity to define a new system with few legacy constraints. The FPGA design engineer will work with systems teams to define/develop/implement/test/release FPGA based solutions to enable LEO. This will focus on creating digital designs for networking functions using the latest generations of FPGA technologies and modern FPGA design processes and tools.

In This Role You Will

• Have ownership of one or more FPGA bitstreams. Create and release FPGAs through the development phases of uArchitecture-RTL Design-Physical Implementation-Timing Closure–Simulation Validation– Lab Based Silicon Validation
• Collaborate with network communication system architects to define and design/implement/test/release/support networking functions targeted to FPGA technology
• Collaborate with Digital Communications/Networking system architects and design engineers to implement digital logic functions in FPGAs.
• Collaborate with system architects and design engineers to implement digital logic functions in FPGA prototypes to validate/tradeoff architecture & design alternatives
• Collaborate with systems architects, HW engineering design teams & FW/SW design teams to bring up and test systems combining FPGA, firmware, RF, and Networking functions.
• Drive trade-off analysis to benefit customer experience and optimization of target technology resources for cost/size/power/performance/features

Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Key job responsibilities

• Design, develop, and implement complex FPGA architectures using Verilog HDL
• Lead FPGA design efforts for Versal ACAP and IGLOO2 platforms from concept through production
• Develop and optimize RTL code for high-performance, resource-efficient designs
• Perform timing analysis, synthesis, place and route, and design verification
• Create comprehensive test benches and simulation environments
• Collaborate with cross-functional teams including hardware engineers, software developers, and system architects
• Debug and troubleshoot FPGA designs at both simulation and hardware levels
• Develop technical documentation including design specifications, test plans, and user guides
• Support hardware integration, manufacturing, and production deployment activities

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field
• 7+ years of FPGA design experience
• Experience with AMD Xilinx Versal ACAP FPGA architecture and development tools
• Demonstrated expertise with Microchip IGLOO2 FPGA platform
• Strong proficiency in Verilog HDL for RTL design and verification
• Experience with FPGA design tools (Vivado, Libero SoC, or equivalent)
• Solid understanding of digital design principles, timing analysis, and clock domain crossing
• Experience with simulation tools (ModelSim, VCS, or similar)
• Strong debugging and problem‑solving skills
• HDL Languages: Verilog (required), SystemVerilog (preferred)
• FPGA Platforms: Versal ACAP, IGLOO2
• Design Tools: Xilinx Vivado, Microchip Libero SoC
• Simulation: ModelSim, Vivado Simulator, or equivalent
• Scripting: Python, TCL, or Perl for design automation
• Protocols: Understanding of industry‑standard communication protocols

Preferred Qualifications

• Experience with SystemVerilog and UVM methodologies
• Knowledge of high‑speed interfaces (PCIe, DDR, Ethernet, SerDes)
• Familiarity with embedded systems and hardware‑software integration
• Experience with version control systems (Git, SVN)
• Background in signal processing, communications, or related applications
• Experience with DO‑254 or other safety‑critical design standards

Amazon Equal Opportunity

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.

Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.

Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.

USA, WA, Redmond - 159,200.00 - 215,300.00 USD annually

Company - Amazon Kuiper Manufacturing Enterprises LLC

Job ID: A3183359