Senior FPGA & Embedded Systems Engineer (TS/SCI)

SAIC; College Park (MD); On-site; USD 200,000 - 240,000; Full time

Job summary

SAIC seeks an experienced FPGA/Embedded-Systems Engineer to design, verify, and integrate advanced digital processing architectures. Strong FPGA development with VHDL and Verilog, plus embedded software skills, are essential for delivering production-ready designs on Linux-based workflows.

The role involves developing DSP algorithms, working with SDR platforms such as Ettus USRP and Pluto SDR, and using Xilinx Vivado/Vitis toolchains for timing closure and IP integration.

Qualifications

• Experience in designing FPGA architectures and verification.
• Proficiency with VHDL/Verilog and Xilinx toolchains.
• Embedded software experience and DSP awareness.

Responsibilities

• Design FPGA architectures for Xilinx UltraScale+ MPSoC and Versal.
• Develop self-checking testbenches and simulation environments.
• Automate toolflows with Tcl/shell scripting.
• Implement high-throughput streaming paths and timing constraints.
• Debug FPGA and embedded software across Linux workflows.
• Collaborate on SDR platforms (Ettus USRP, Pluto SDR) for system-level development.
• Develop DSP algorithms when required and integrate with FPGA logic.
• Maintain source control with Git and support CI workflows.

Skills

HDL design

VHDL

Verilog

Embedded C/C++

Python

Linux

DSP

Xilinx Vivado

Vitis

IP integration

Education

Bachelor’s degree +14 yrs

Master’s degree +12 yrs

PhD/JD +9 yrs

Tools

ModelSim

Riviera Pro

XSim

Yocto

Git

Shell scripting

Tcl scripting

Bash

Job description

SAIC seeks an experienced FPGA/Embedded-Systems Engineer to design, verify, and integrate advanced digital processing architectures. Strong FPGA development with VHDL and Verilog, plus embedded software skills, are essential for delivering production-ready designs on Linux-based workflows.

The role involves developing DSP algorithms, working with SDR platforms such as Ettus USRP and Pluto SDR, and using Xilinx Vivado/Vitis toolchains for timing closure and IP integration.