Senior FPGA DSP/HW Design Engineer (TS/SCI)

Aperio Global; Fort Meade (MD); On-site; USD 130,000 - 230,000; Full time

Benefits offered by this job

Health insurance

401k match

Life insurance

Paid time off

Disability insurance

Professional development

Job summary

Aperio Global is seeking an experienced senior HW/SW Design Engineer to design, develop, and test FPGA-based hardware and software processing components for RF communication and collection systems at Fort Meade, MD.

The role combines FPGA RTL development, DSP algorithm implementation, Linux integration, and hardware/Software co-design to deliver complete subsystem solutions. Active TS/SCI with Polygraph is required.

Qualifications

• Bachelor's degree plus 8 years of relevant experience or equivalent.
• Active TS/SCI with Polygraph required.
• Vivado experience preferred; Epiq Solution PDK experience a plus.

Responsibilities

• Lead hardware design efforts: FPGA RTL, timing closure, and DSP integration.
• Implement DSP algorithms and connect FPGA components with Linux-based software.
• Bridge FPGA-to-software stack and document system-level design decisions.

Skills

FPGA coding

DSP theory & application

Linux OS

C/C++ coding

Software-hardware integration

Education

Bachelor's degree + 8 years relevant experience

Tools

Vivado

Epiq Solution PDK

Job description

Aperio Global is seeking an experienced senior HW/SW Design Engineer to design, develop, and test FPGA-based hardware and software processing components for RF communication and collection systems at Fort Meade, MD.

The role combines FPGA RTL development, DSP algorithm implementation, Linux integration, and hardware/Software co-design to deliver complete subsystem solutions. Active TS/SCI with Polygraph is required.