Senior FPGA Design Architect - USB/Ethernet PHY

Microchip Technology Inc; Chandler (AZ); On-site; USD 120,000 - 170,000; Full time

Job summary

Microchip Technology Inc in Chandler, AZ is seeking an experienced FPGA Design Engineer to support USB and Ethernet PHY platforms. The role focuses on RTL development, FPGA synthesis, timing, and system integration across digital, analog, and software teams.

Located at the Chandler Design Center, you will collaborate across hardware, firmware, software, and verification groups to deliver robust FPGA-based solutions.

Qualifications

• 10+ years of FPGA/digital design experience with RTL, simulation, synthesis, and hardware implementation.
• Strong RTL coding in Verilog or SystemVerilog for synthesizable designs.
• Solid understanding of state machines, datapaths, pipelines, clocks, resets, FIFOs, memories, and interface logic.
• Experience developing self-checking testbenches and functional simulation.
• Experience with FPGA synthesis/implementation and timing analysis in vendor tools.
• Ability to design multi-clock-domain timing constraints and architectures.
• Experience integrating FPGA systems and board bring-up.
• Proficiency with lab equipment: oscilloscopes, logic analyzers, protocol analyzers; debugging hardware.
• Collaborative work with hardware, firmware, software, ASIC, verification teams.
• Knowledge of USB and Ethernet PHY architectures is a plus.
• Document FPGA requirements, architecture, diagrams, and interface specs.
• Scripting (TCL, Python, Perl; Linux shell) and programming (C++ or Rust) for automation.
• Experience with version control (Perforce, Git, DesignSync).
• Strong verbal and written communication skills.

Skills

FPGA design

RTL coding

Verilog SystemVerilog

clock domain crossing

timing optimization

self-checking testbenches

lab bring-up

hardware software collaboration

communication skills

USB Ethernet PHY knowledge

Tools

QuestaSim/ModelSim

AMD/Xilinx Vivado

Job description

Microchip Technology Inc in Chandler, AZ is seeking an experienced FPGA Design Engineer to support USB and Ethernet PHY platforms. The role focuses on RTL development, FPGA synthesis, timing, and system integration across digital, analog, and software teams.

Located at the Chandler Design Center, you will collaborate across hardware, firmware, software, and verification groups to deliver robust FPGA-based solutions.