Senior FPGA Architect & Lead for AI & Server Platforms

Jabil; Austin (TX); On-site; USD 120,000 - 170,000; Full time

Job summary

Jabil is seeking an FPGA Lead Engineer in Austin to lead FPGA design, integration, and debugging for server, storage, and AI infrastructure platforms. You will own FPGA architecture, RTL implementation, and verification readiness while coordinating with systems, firmware, and manufacturing teams.

The role requires strong leadership, deep FPGA toolchain experience (Xilinx/Intel), and hands-on debugging across FPGA, PCB, and HW bring-up cycles.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering or related field; Master’s degree preferred.
• 5–10 years of FPGA design, programmable logic development, hardware integration, or related platform engineering work.
• Strong expertise in FPGA design flows, RTL development, simulation, timing analysis, constraints, and lab-based debug.
• Experience with AMD/Xilinx, Intel/Altera toolchains; knowledge of interfaces like SPI, I2C, UART, Ethernet, PCIe, JESD.

Responsibilities

• Technical Leadership: Lead development teams, conduct design reviews, and oversee requirement traceability.
• Hardware Validation: Lead debugging and testing campaigns on PCBs using lab equipment (oscilloscopes, logic analyzers, function generators).
• Project Management: Plan and manage technical, cost, and schedule objectives; monitor risks and configuration.
• Own investigation and closure of complex FPGA, hardware, and firmware issues during bring-up and ramp.
• Collaborate with Electrical, BIOS, BMC, Systems, Validation, Manufacturing, and customers to resolve cross-domain issues.
• Support FPGA verification readiness, lab debug, hardware validation, and release criteria by ensuring traceability.
• Mentor junior engineers and contribute to reusable design practices, documentation quality, and engineering best practices.
• Communicate technical direction and risk to leadership, customers, and cross-functional stakeholders.

Skills

FPGA design flows

RTL development

Simulation

Timing analysis

Constraints

Lab-based debug

Technical leadership

Effective communication

Education

Bachelor’s degree in Electrical/Computer Engineering or related field

Master’s degree preferred

Tools

FPGA toolchains (Xilinx/Intel)

Job description

Jabil is seeking an FPGA Lead Engineer in Austin to lead FPGA design, integration, and debugging for server, storage, and AI infrastructure platforms. You will own FPGA architecture, RTL implementation, and verification readiness while coordinating with systems, firmware, and manufacturing teams.

The role requires strong leadership, deep FPGA toolchain experience (Xilinx/Intel), and hands-on debugging across FPGA, PCB, and HW bring-up cycles.