Senior Foundry Interface Engineer — Yield Leadership + Equity

SiTime Corp.; Santa Clara (CA); Hybrid; USD 148,000 - 204,000; Full time

Benefits offered by this job

401k plan

Health and wellness benefits

Equity grants

Time off plans

Job summary

SiTime Corp. is seeking a Principal Foundry Interface Engineer in Santa Clara, CA. The role focuses on supporting Foundry interface, driving yield improvements and coordinating with multiple foundries to ensure on-time wafer delivery.

The candidate will use AI/ML predictive modeling and in-depth data analysis to project test-chip yields and guide process health monitoring, while leading cross-functional teams.

Qualifications

• Master’s degree with 13+ years of industry experience in semiconductor process integration or related field.
• PhD with 10+ years of experience in semiconductor-related research or engineering.
• Proven track record in yield Pareto construction, modeling and roadmaps.

Responsibilities

• Lead Foundry yield improvement and mitigate yield detractors.
• Manage yield excursions and implement Continuous Improvement Plans.
• Provide technical guidance on Foundry Fab transfer projects.
• Direct wafer lot progress, DOEs, and process skew strategies.
• Communicate process health and drive on-time wafer output from the fab.

Skills

Yield optimization

Foundry collaboration

AI/ML modeling

Process integration

Data analysis

Education

Master’s degree in engineering/physical science

PhD in relevant field

Tools

PDF Exensio

Job description

SiTime Corp. is seeking a Principal Foundry Interface Engineer in Santa Clara, CA. The role focuses on supporting Foundry interface, driving yield improvements and coordinating with multiple foundries to ensure on-time wafer delivery.

The candidate will use AI/ML predictive modeling and in-depth data analysis to project test-chip yields and guide process health monitoring, while leading cross-functional teams.