Senior Flip-Chip Process Engineer, Silicon Photonics

Uncover; San Jose (CA); Hybrid; USD 140,000 - 190,000; Full time

Benefits offered by this job

Health insurance

Job summary

Lumilens in San Jose is seeking a Senior/Staff Process Engineer to own the Flip Chip process for silicon photonic wafers. You will lead DOE, material qualification, and reliability tests while optimizing process integration with upstream steps.

The role requires 5+ years in flip chip assembly, expertise in plasma cleaning, flux engineering, and FEM-based warpage analysis, plus strong problem-solving and SPC skills. On-site role in San Jose, CA.

Qualifications

• Bachelor’s or Master’s degree in Materials Science, Chemical Engineering, Mechanical Engineering, or Microelectronics.
• 5+ years hands-on experience in flip chip assembly.
• Deep practical knowledge of flip chip processes (plasma cleaning, flux, reflow, underfill).
• Experience with FEM for warpage, thermal dissipation, and structural integrity.
• FMEA, SPC controls and 8D problem solving.
• Proficiency with JMP or Minitab.

Responsibilities

• Own process development and technical support of Flip Chip for silicon photonic wafers.
• Design and run DOE to characterize process window and margin.
• Evaluate and qualify new manufacturing materials.
• Lead reliability validations (TCT, HAST, HTS).
• Perform failure analysis and implement improvements.
• Establish SPC control plans and monitor process variation.
• Prepare SOPs, WIs, and change documents; support NPI.

Skills

Flip-chip assembly

Process development

DOE planning

Root-cause analysis

FMEA

8D problem solving

SPC controls

JMP

Minitab

Thermal/warpage analysis

Education

Bachelor’s or Master’s degree in Materials Science / related field

Tools

JMP

Minitab

Job description

Lumilens in San Jose is seeking a Senior/Staff Process Engineer to own the Flip Chip process for silicon photonic wafers. You will lead DOE, material qualification, and reliability tests while optimizing process integration with upstream steps.

The role requires 5+ years in flip chip assembly, expertise in plasma cleaning, flux engineering, and FEM-based warpage analysis, plus strong problem-solving and SPC skills. On-site role in San Jose, CA.