Senior/Staff Process Engineer (Flip Chip)

Uncover; San Jose (CA); Hybrid; USD 140,000 - 190,000; Full time

Benefits offered by this job

Health insurance

Job summary

Lumilens in San Jose is seeking a Senior/Staff Process Engineer to own the Flip Chip process for silicon photonic wafers. You will lead DOE, material qualification, and reliability tests while optimizing process integration with upstream steps.

The role requires 5+ years in flip chip assembly, expertise in plasma cleaning, flux engineering, and FEM-based warpage analysis, plus strong problem-solving and SPC skills. On-site role in San Jose, CA.

Qualifications

• Bachelor’s or Master’s degree in Materials Science, Chemical Engineering, Mechanical Engineering, or Microelectronics.
• 5+ years hands-on experience in flip chip assembly.
• Deep practical knowledge of flip chip processes (plasma cleaning, flux, reflow, underfill).
• Experience with FEM for warpage, thermal dissipation, and structural integrity.
• FMEA, SPC controls and 8D problem solving.
• Proficiency with JMP or Minitab.

Responsibilities

• Own process development and technical support of Flip Chip for silicon photonic wafers.
• Design and run DOE to characterize process window and margin.
• Evaluate and qualify new manufacturing materials.
• Lead reliability validations (TCT, HAST, HTS).
• Perform failure analysis and implement improvements.
• Establish SPC control plans and monitor process variation.
• Prepare SOPs, WIs, and change documents; support NPI.

Skills

Flip-chip assembly

Process development

DOE planning

Root-cause analysis

FMEA

8D problem solving

SPC controls

JMP

Minitab

Thermal/warpage analysis

Education

Bachelor’s or Master’s degree in Materials Science / related field

Tools

JMP

Minitab

Job description

# Senior/Staff Process Engineer (Flip Chip)Lumilens • San Jose, CA • • 2h agoSave this role or tell us whether you want more jobs like it.**Core Responsibilities**1. Owns the process development and technical support of the Flip Chip process for silicon photonic chip wafers, with OSAT or internal line. Process may include plasma cleaning, flux engineering, pick & place, reflow, underfill, curing and/or TCB/NCP flux-less flow.2. DOE to characterize process window and margin. Optimize process integration with upstream processes (e.g. bump/FO) to increase yield and manufacturability.3. Material Characterization & Selection: Evaluate and qualify new manufacturing raw materials, including NCP, flux, underfill etc, as applicable.4. Design and execute DOE plans to characterize thermal and mechanical stress. Lead reliability validations including Temperature Cycling Test (TCT), Unbiased Highly Accelerated Stress Test (HAST) and High-Temperature Storage (HTS).5. Failure Analysis & Debug: Own the root-cause diagnostics of structural failure modes unique to FC (e.g. flux void, residue, misalignment, die warpage, reflow anomaly, underfill void etc), and formulate improvement solutions.6. Manage incoming material quality control, establish SPC control plans and monitor process variation to ensure long-term process stability.7. Compile process SOP, WI, process failure reports and engineering change documents; support NPI new product introduction and process verification.**Key Requirements & Qualifications*** Education: Bachelor or Master degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or an equivalent technical discipline.* Experience: 5+ years of hands-on industry experience in flip chip assembly.* Technical Knowledge:* Deep practical understanding of plasma cleaning, flux engineering, pick & place, reflow, underfill, curing and/or TCB/NCP flux-less flow.* Comprehensive command of finite element simulation principles regarding warpage, thermal dissipation, and structural mechanical integrity.* Solid working expertise with industry validation methodologies including FMEA, SPC controls, and structured 8D problem-solving tools.* Software Tools: High proficiency with robust analytical platforms like JMP, Minitab.