Senior ESD & Reliability Tools Engineer

Intel Corporation

Santa Clara (CA)

On-site

USD 150,000 - 285,000

Full time

9 days ago

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Job summary

Intel Corporation is seeking a senior ESD/PDK engineer to develop PERC ESD rule decks for cutting-edge process technologies. You will collaborate with design, reliability, and CAD teams and with external EDA vendors to implement new tool features and ensure robust rule checks.

The role emphasizes innovation, automation, and cross-site teamwork across a fast-paced semiconductor environment. The position is housed within Intel's Design Technology Platform and offers on-site work with opportunities

Qualifications

Master's degree or PhD in Electrical Engineering or Computer Engineering.
2+ years' experience with ESD PERC rule decks/runset development and debugging.
2+ years' experience in scripting (Python, Tcl, Perl, or similar) for QA and flow automation.

Responsibilities

Develop ESD/LU rule decks aligned with the ESD Design Rule Manual (DRM) and reliability requirements.
Create and maintain reliability ESD and LU design rule methodologies and specifications.
Collaborate with internal design, reliability, and CAD teams as well as external EDA vendors to define and implement new tool features and requirements.
Build and execute test cases for rule debugging, validation, and signoff.
Define QA requirements and drive related automation to improve robustness and efficiency of rule checks.
Lead innovation initiatives to enhance existing ESD/LU verification automation, tools, and methodologies.
Identify and analyze ESD/LU design problems, define root causes, and drive practical solutions across teams.