Senior Engineer RTL Power Macro Modeling

Conductor; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Benefits offered by this job

4+ weeks paid time off

Fertility care stipend

Medical travel support

Onsite Café & gym

Job summary

Conductor in San Jose, CA seeks an engineer to develop power and energy macromodels for die-to-die PHY and 2.5D interposer interconnect in C-HBM programs. The role builds these models from S-parameter models, calibrates them against circuit references, and makes them fast enough to run over long workload traces.

Located onsite daily in San Jose with a direct report to the SVP, R&D (Power & Thermal Lab), you will deliver validated models and collaborate with software engineers on model interfaces.

Qualifications

• Bachelor’s degree in EE/CS with 5+ years’ experience, or MS with 3+ years, or PhD with 0 years.
• Strong Python for numerical computing.
• Familiarity with S-parameters and frequency-domain network analysis.
• Experience with SPICE-level circuit simulation.
• Understanding of dynamic switching power in CMOS drivers and interconnect.
• Ability to abstract circuit behavior into compact analytical or table-based models.
• Familiarity with RTL/SystemC simulation flows and how power models are used.
• Excellent technical writing and verbal communication skills.

Responsibilities

• Develop energy and power macromodels of interposer interconnect and PHY transmit front-ends from S-parameter models of the channel.
• Extract per-lane self-capacitance and inter-lane mutual capacitance from the network parameters, and relate them to switching energy.
• Build a circuit-level reference in SPICE and use it to calibrate the macromodels and bound their error.
• Develop and compare reduced-order model forms, and select among them by measured accuracy.
• Design calibration stimuli and parameter-extraction procedures.
• Ensure models evaluate efficiently over wide buses and long workload traces.
• Analyze sensitivity to data pattern, bus encoding, activity factor, and operating point.
• Extend the modeling approach to additional interfaces and interconnect structures as the program scope grows.
• Deliver validated models and regression checks into the trace-driven simulation pipeline, and collaborate with software engineers on model interfaces.

Skills

Python

S-parameters

CMOS power

Modeling

SPICE

RTL/SystemC

Thermal engineering

Data analysis

Education

Bachelor's degree in EE/CS

MS/PhD preferred

Tools

SPICE

PrimeTime PX

StarRC

Verdi

Job description

San Jose, California, United States

Advancing the World’s Technology Together

Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

Role Summary

We are seeking an engineer to develop power and energy macromodels for die-to-die (D2D) PHY and 2.5D interposer interconnect in C-HBM programs. The role builds these models from S-parameter models of the interconnect, calibrates them against circuit-level references, and makes them fast enough to run over long workload traces. The resulting models feed time-indexed power maps into the trace-driven power and thermal simulation flow.

Location: Daily onsite presence at our San Jose, CA in alignment with our Flexible Work policy

Reports to: SVP, R&D (Power & Thermal Lab)

What You’ll Do

• Develop energy and power macromodels of interposer interconnect and PHY transmit front-ends from S-parameter models of the channel.
• Extract per-lane self-capacitance and inter-lane mutual capacitance from the network parameters, and relate them to switching energy.
• Build a circuit-level reference in SPICE and use it to calibrate the macromodels and bound their error.
• Develop and compare reduced-order model forms, and select among them by measured accuracy.
• Design calibration stimuli and parameter-extraction procedures.
• Ensure models evaluate efficiently over wide buses and long workload traces.
• Analyze sensitivity to data pattern, bus encoding, activity factor, and operating point.
• Extend the modeling approach to additional interfaces and interconnect structures as the program scope grows.
• Deliver validated models and regression checks into the trace-driven simulation pipeline, and collaborate with software engineers on model interfaces.

What You Bring

• Bachelors degree with 5+ years of experience or Masters degree with 3+ years of experience preferred or PhD Degree with 0 years of experience.
• Strong Python for numerical and scientific computing.
• Proven self-discipline and professional maturity to execute independent research and meet rigorous milestones with a strong sense of accountability for both personal and collective goals in a fast-paced, on-site environment.
• Familiarity with S-parameters and frequency-domain network analysis.
• Experience with SPICE-level circuit simulation.
• Understanding of dynamic switching power in CMOS drivers and interconnect, including coupling capacitance.
• Ability to abstract circuit behavior into compact analytical or table-based models.
• Familiarity with RTL/SystemC simulation flows and how power models are used in them.
• Deep knowledge and experience in Thermal Engineering.
• Expertise in FloTHERM and familiarity with other CFD tools.
• Excellent technical writing and verbal communication skills for collaboration, documentation, and presentations.

Preferred Qualifications

Exposure to UCIe or other die-to-die interfaces, high-speed I/O, or 2.5D packaging.

Hands-on experience with power analysis tools such as PrimeTime PX, StarRC, or Verdi.

Experience running large parameter sweeps or parallelized analysis.

Prior experience in power or thermal modeling.

What We Offer

The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience. We also offer incentive opportunities that reward employees based on individual and company performance.

This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.

Give Back: With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.

Enjoy Time Away: You’ll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.

Care for Family: Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.

Prioritize Emotional Wellness: With on-demand apps and free confidential therapy sessions, you’ll have support no matter where you are.

Stay Fit: Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.

Embrace Flexibility: Benefits are best when you have the space to use them. That’s why we facilitate a flexible environment so you can find the right balance for you.

Base Pay Range

$138,000 - $206,000 USD

Equal Opportunity Employment Policy

Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.

When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.

Our Commitment to Innovation and Fairness

At Samsung Semiconductor, we use Artificial Intelligence (AI) tools in the recruitment process to enhance efficiency. However, AI is used as a support tool, not a final decision-maker. All hiring decisions are made by our human recruiting team and hiring managers to ensure every candidate is evaluated fairly and holistically.

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At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we ask that candidates rely on their own knowledge and skills throughout the process. AI tools may be used for basic preparation, grammar, and research, but should not be used to generate or assist with submitted content or live interview responses. If we determine that AI is being used outside these guidelines, we reserve the right to pause or end the interview, and your candidacy may be disqualified.

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