Senior Emulation Performance Architect & Debug

Qualcomm; Hillsboro (OR); On-site; USD 122,000 - 183,000; Full time

Job summary

Qualcomm Technologies, Inc. seeks a Senior Emulation Performance Methodology & Debug Engineer to lead emulation methodology across FPGA platforms and pre-silicon validation. You will work with architects, designers, and customers to ensure robust SoC development.

The role requires deep Verilog/SystemVerilog expertise, emulation tool proficiency, and collaboration across sites. Strong debugging and Python/TCL scripting skills are expected.

Qualifications

• Bachelor's degree in Science, Engineering, or related field with 4+ years of ASIC experience.
• Alternatively Master's with 3+ years; PhD with 2+ years in ASIC design/verification.
• Preferred emulation and pre-silicon prototyping experience.

Responsibilities

• Develop and maintain emulation methodologies across FPGA-based platforms.
• Collaborate across teams: architects, designers, verifiers, and customers.
• Debug and validate SoC functionality; support pre-silicon bring-up.
• Utilize emulation platforms (FPGA, Veloce, Palladium) and related tools.

Skills

Verilog/SystemVerilog

Python

C programming

FPGA Prototyping

Timing closure

Software debugging

Education

Bachelor's degree in Science, Engineering

Master's degree in Science, Engineering

PhD in Science, Engineering

Tools

FPGA Prototyping

Veloce

Palladium

Synthesis

Place and Route

Xilinx FPGAs

Intel FPGAs

Job description

Qualcomm Technologies, Inc. seeks a Senior Emulation Performance Methodology & Debug Engineer to lead emulation methodology across FPGA platforms and pre-silicon validation. You will work with architects, designers, and customers to ensure robust SoC development.

The role requires deep Verilog/SystemVerilog expertise, emulation tool proficiency, and collaboration across sites. Strong debugging and Python/TCL scripting skills are expected.