Senior DRAM Process Integration Engineer (Onsite)

samsungsemiconductor; San Jose (CA); Presencial; USD 163.000 - 253.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Paid time off (4+ weeks)

Fertility/adoption support stipend

Confidential therapy sessions

Onsite café and gym

Flexible work environment

401(k) and comprehensive benefits

Descripción de la vacante

Samsung Semiconductor Inc. seeks a Process Integration Engineer to advance DRAM technology. You will design, integrate, and optimize fabrication processes for next‑gen memory devices at our San Jose campus, collaborating across engineering, quality, and design teams.

The role requires deep experience in DRAM/NAND memory development with strong DoE and data analysis skills, plus a proven ability to drive complex integration projects onsite under a flexible work policy.

Formación

• BS in a relevant field with 10+ years industry experience (preferred).
• MS with 8+ years industry experience (preferred).
• PhD with 5+ years industry experience (preferred).

Responsabilidades

• Plan, design, and implement process integration for future DRAM wafer fabrication.
• Define technology requirements, design rules, and electrical specs.
• Execute technology integration in memory components and CMOS devices.
• Identify module requirements and drive cross-functional teams.
• Engage with cross-function teams to meet product requirements.
• Progress process module development and full process integration.
• Interact with internal and external customers on technical matters.
• Analyze inspection and measurement data to improve performance.

Conocimientos

DRAM memory R&D

Process integration

DoE principles

Statistical data analysis

Cross-functional collaboration

Educación

BS in a related field

MS in a related field

PhD in a related field

Descripción del empleo

Samsung Semiconductor Inc. seeks a Process Integration Engineer to advance DRAM technology. You will design, integrate, and optimize fabrication processes for next‑gen memory devices at our San Jose campus, collaborating across engineering, quality, and design teams.

The role requires deep experience in DRAM/NAND memory development with strong DoE and data analysis skills, plus a proven ability to drive complex integration projects onsite under a flexible work policy.