Senior DRAM Design Readiness Lead

Micron Technology, Inc; Boise (ID); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Robust paid time off

Paid holidays

Job summary

Micron Technology, Inc. is seeking a Sr Design Readiness Engineer to lead design readiness activities for DRAM products.

You will partner with cross-functional teams to define validation coverage, prioritize debug activities, and drive root-cause investigations using silicon data and statistical methods. The role emphasizes mentorship, improving readiness processes, and influencing design decisions across DRAM programs.

Qualifications

• Advanced degree in Electrical/Computer/Semiconductor engineering, or equivalent industry experience.

Responsibilities

• Lead design readiness activities for new DRAM products, including risk assessments, DFMEA development, validation planning, and readiness reviews.
• Partner with cross-functional teams to identify product risks, define validation coverage, and prioritize debug activities.
• Drive root-cause investigations of silicon findings through data analysis, experiment planning, evidence review, and corrective action development.
• Influence product readiness decisions by connecting design intent, validation results, silicon behavior, manufacturing constraints, and customer quality expectations.
• Mentor engineers and help improve technical practices, readiness processes, and organizational learning across DRAM programs.

Skills

Semiconductor design

DRAM/memory technology

Silicon validation

Data analysis

Root-cause analysis

Cross-functional collaboration

Communication

Education

Advanced degree in Electrical/Computer/ Semiconductor Engineering

PhD or MS in a relevant field

Tools

AI-enabled engineering analysis tools

Statistical analysis tools

Job description

Micron Technology, Inc. is seeking a Sr Design Readiness Engineer to lead design readiness activities for DRAM products.

You will partner with cross-functional teams to define validation coverage, prioritize debug activities, and drive root-cause investigations using silicon data and statistical methods. The role emphasizes mentorship, improving readiness processes, and influencing design decisions across DRAM programs.