Senior DRAM Innovation & Automation Engineer

Micron Technology Inc; Boise (ID); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off

Competitive 401(k)

Job summary

Micron Technology is seeking an experienced engineer to design, verify, and optimize memory and related circuits across advanced technology nodes. You will own major data path blocks, lead cross-functional initiatives, and drive AI-enabled automation to improve yield and performance.

The role requires strong technical leadership with experience in DRAM/NAND interfaces and a proven track record in silicon verification and layout optimization.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering or Physics (emphasis on semi electronics) or equivalent.
• Senior: 2–5 years of relevant experience.
• Principal: 8+ years of relevant experience.
• Experience with DRAM, NAND, Logic, or related interfaces.

Responsibilities

• Design, analyze, and verify memory, logic, and analog circuits across advanced technology nodes.
• Own and support major data path blocks including Sense Amplifiers, timing distribution, calibration, and training features.
• Identify design marginalities and recommend circuit-level or architectural solutions to improve DRAM robustness, yield, and performance.
• Enable new process node startup, qualification, yield learning, and production ramp.
• Provide technical guidance to Technology Development teams using strong process and device integration knowledge.
• Develop and track key metrics to assess technology readiness.
• Support design verification and validation using CAD tools, modeling, and simulation.
• Define and execute silicon experiments and debug strategies in collaboration with Product Engineering.
• Perform electrical failure analysis of DRAM Array Sensing Schemes and lead yield improvement initiatives using statistical analysis.
• Guide Sense Amp layout activities including floor planning, placement, routing, and layout reviews.
• Perform parasitic extraction and modeling to optimize signal margin and memory bit interaction of Sense Amps and Wordline drivers.
• Drive layout-aware optimization decisions to improve scalability and manufacturability.
• Collaborate with Design, Technology Development, DFT, Test, Reliability, Quality, Manufacturing, Probe, Assembly, and Marketing teams.
• Partner with Applications Engineering to evaluate specifications and balance customer requirements with design and process constraints.
• Leverage AI-based tools, automation, and advanced analytics to improve design quality, yield learning, and workflow efficiency.
• Drive innovation for future memory generations.
• Document methodologies clearly, present results to technical forums and leadership, mentor junior engineers, and lead complex cross-functional initiatives.

Skills

Strong communication

Technical leadership

AI in engineering workflows

Education

Bachelor’s degree in Electrical or Computer Engineering or Physics (emphasis on semiconductor electronics)

Master’s degree in Electrical or Computer Engineering or Physics (emphasis on semiconductor electronics)

Tools

CAD tools

Modeling

Parasitic extraction

Job description

Micron Technology is seeking an experienced engineer to design, verify, and optimize memory and related circuits across advanced technology nodes. You will own major data path blocks, lead cross-functional initiatives, and drive AI-enabled automation to improve yield and performance.

The role requires strong technical leadership with experience in DRAM/NAND interfaces and a proven track record in silicon verification and layout optimization.