Senior DRAM Verification Design Engineer

1000 Micron Technology, Inc.; Boise (ID); Presencial; USD 110 000 - 160 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Medical, dental & vision

Paid time off

Holidays & leaves

Resumo da oferta

Micron Technology seeks a verification engineer to shape verification strategies for DRAM products, collaborating with design, product engineering, test, and process integration to ensure performance, quality and reliability.

Join a team that drives verification from gate-level to full‑chip implementations, develops verification plans, analyzes parasitics, and mentors engineers across global sites, using industry-standard tools and methodologies.

Qualificações

• Bachelor’s degree in Electrical Engineering or Computer Engineering.
• 5+ years of experience in verification or related design roles.
• Strong background in semiconductor circuit design, modeling, and verification.
• Strong understanding of DRAM/memory architecture and verification challenges.
• Proficiency with HSPICE and Python.

Responsabilidades

• Contribute to the design and drive the verification of memory circuits from gate-level to full chip implementations.
• Develop and execute verification plans for advanced DRAM builds.
• Lead circuit- and system-level verification using industry-standard tools and methodologies.
• Drive verification of memory arrays, control logic, address decode, data paths, and internal test logic.
• Analyze layout-extracted parasitics and guide critical circuit reviews.

Conhecimentos

HSPICE

Python

DRAM architecture

DFT methodologies

RTL verification

STA

Timing Verilog

Silicon validation

Formação académica

Bachelor’s degree in Electrical Engineering or Computer Engineering

Descrição da oferta de emprego

Micron Technology seeks a verification engineer to shape verification strategies for DRAM products, collaborating with design, product engineering, test, and process integration to ensure performance, quality and reliability.

Join a team that drives verification from gate-level to full‑chip implementations, develops verification plans, analyzes parasitics, and mentors engineers across global sites, using industry-standard tools and methodologies.