Senior Director, AMS Layout Engineering — 100G+ SerDes

Upscale, Inc.; Santa Clara (CA); On-site; USD 306,000 - 337,000; Full time

Job summary

Upscale, Inc. is building the high-performance infrastructure powering the next generation of artificial intelligence.

As Senior Director of AMS Layout Engineering, you will lead the physical implementation of advanced high-speed analog and mixed-signal circuits for next-generation SerDes technologies. This strategic technical leadership role requires deep expertise in advanced-node analog layout, a strong understanding of high-speed PHY design challenges, and a proven track record of building

Qualifications

• BS, MS, or PhD in Electrical Engineering, Microelectronics, or a related field.
• Proven experience delivering advanced-node analog or mixed-signal designs at 5nm or below, or equivalent leading-edge process technologies.
• Strong understanding of layout techniques for high-speed SerDes and PHY circuits, including high-speed transmitters, receivers, clocking circuits, PLLs, DLLs, and other timing-critical analog blocks.
• Demonstrated understanding of advanced process design rules, parasitic extraction, physical verification, device matching, signal integrity, and power integrity.
• Experience leading complex silicon development programs from early floorplanning and layout planning through physical verification, tape-out, and silicon bring-up.
• Proven ability to recruit, develop, mentor, and retain strong engineering talent while building an effective and collaborative team.
• Excellent communication skills and the ability to influence technical decisions across multidisciplinary engineering organizations.

Responsibilities

• Technical Leadership: Lead AMS layout engineering for advanced high-speed SerDes PHYs, driving physical implementation, optimization, and sign-off across critical analog and mixed-signal circuit blocks.
• Advanced-Node Expertise: Drive layout solutions at advanced nodes, addressing increasingly complex design rules, restrictive patterning requirements, parasitic effects, device matching, signal integrity, power integrity, and electromigration.
• High-Speed PHY Optimization: Partner with circuit designers to optimize layout-sensitive performance, including bandwidth, jitter, noise, matching, power consumption, and overall silicon robustness at 100G+ per-lane data rates.
• Physical Design Methodology: Establish and improve layout methodologies, design guidelines, verification flows, and quality standards to enable predictable execution and first-silicon success.
• Cross-Functional Collaboration: Work closely with AMS design, digital implementation, technology, package, and silicon validation teams to resolve complex integration challenges and deliver competitive silicon.
• Organization Building: Build and scale a strong AMS layout organization through strategic hiring, technical mentorship, talent development, and succession planning.
• Execution and Delivery: Drive project planning, resource allocation, technical reviews, and execution across multiple concurrent development efforts while maintaining high standards for quality, schedule, and engineering productivity.
• Engineering Excellence: Foster a culture of technical depth, accountability, continuous improvement, and collaboration across geographically distributed teams.

Education

BS, MS, or PhD in Electrical Engineering, Microelectronics, or a related field

Job description

Upscale, Inc. is building the high-performance infrastructure powering the next generation of artificial intelligence.

As Senior Director of AMS Layout Engineering, you will lead the physical implementation of advanced high-speed analog and mixed-signal circuits for next-generation SerDes technologies. This strategic technical leadership role requires deep expertise in advanced-node analog layout, a strong understanding of high-speed PHY design challenges, and a proven track record of building