Senior Digital Verification Engineer – Gate-Level ASIC/FPGA

Mission Technologies, a division of HII; Fort Meade (MD); On-site; USD 116,245 - 190,900; Full time

Job summary

A leading defense technology firm is seeking a Senior Digital Design Verification Engineer in Fort Meade, Maryland. The role involves challenging tasks such as uncovering bugs in gate-level designs and requires extensive experience in verification languages and tools. Candidates must be U.S. citizens with a TS/SCI clearance. Ideal applicants will have strong collaboration skills and a background in cybersecurity and electronic warfare. Position is full-time with a competitive salary range.

Qualifications

• 9 years relevant experience with Bachelor's in related field.
• Experience with digital verification languages and tools.
• Must possess active TS/SCI with Full Scope Poly.

Responsibilities

• Develop models, transactors, and test benches for digital verification.
• Produce documentation and test cases for identified bugs.
• Collaborate effectively with teammates.

Skills

SystemVerilog

SystemC

C/C++

Python

Bash

UVM concepts

ABV techniques

Education

Bachelor's in related field

Master's in related field

High School Diploma or equivalent plus 13 years experience

Tools

Questa

VCS

Ghidra

IDA Pro

Xcelium

Job description

A leading defense technology firm is seeking a Senior Digital Design Verification Engineer in Fort Meade, Maryland. The role involves challenging tasks such as uncovering bugs in gate-level designs and requires extensive experience in verification languages and tools. Candidates must be U.S. citizens with a TS/SCI clearance. Ideal applicants will have strong collaboration skills and a background in cybersecurity and electronic warfare. Position is full-time with a competitive salary range.