Senior Digital Macro Design Engineer

Arm Limited; Seattle (WA); Hybrid; USD 120,000 - 190,000; Full time

Job summary

Arm Limited is seeking a Design Engineer to contribute to digital hard macros across RTL, physical implementation, timing, and verification. You will work on custom and semi-custom macros, build automation flows, and participate in silicon validation, collaborating with SoC teams to optimize macro delivery.

The role emphasizes understanding of layout, circuit behavior, and cross-domain debugging, with hybrid work patterns and a focus on development lifecycle coverage.

Qualifications

• 2–5 years of experience in digital design or Physical IP.
• Strong RTL design fundamentals.
• Hands-on with synthesis, floorplanning, place-and-route, timing closure, and physical verification.
• Familiarity with Cadence Innovus, Tempus, Genus, or equivalents.
• Understanding of timing constraints, SDC, CDC, and multi-clock designs.
• Knowledge of transistor-level concepts and digital circuit operation.
• Experience with Verilog/SystemVerilog and scripting (Tcl or Python).
• Strong analytical, debugging, and teamwork skills.

Responsibilities

• Support design and implementation of custom and semi-custom digital hard macros.
• Develop and maintain RTL, timing constraints, implementation scripts, and automation flows.
• Execute synthesis, floorplanning, place-and-route, timing closure, physical verification, and signoff activities.
• Analyze and debug timing, power, congestion, DRC, LVS, and implementation issues.
• Review schematics and layout structures to understand macro operation and implementation tradeoffs.
• Support functional, gate-level, and mixed-signal simulation activities.
• Assist in characterization activities including timing, power, and functional model validation.
• Generate and validate macro deliverables including Liberty models, LEF abstracts, physical views, and integration collateral.
• Collaborate with AMS, DFT, verification, and SoC integration teams during development and product integration.
• Participate in silicon validation activities and support correlation of silicon behavior with pre-silicon expectations.
• Contribute to methodology improvements, scripting, and automation initiatives.

Skills

RTL design

Synthesis & PnR

Timing closure

Verilog/SystemVerilog

Scripting (Python/Tcl)

Debugging & analytics

Teamwork & communication

Tools

Cadence Innovus

Tempus

Genus

Job description

Arm Limited is seeking a Design Engineer to contribute to digital hard macros across RTL, physical implementation, timing, and verification. You will work on custom and semi-custom macros, build automation flows, and participate in silicon validation, collaborating with SoC teams to optimize macro delivery.

The role emphasizes understanding of layout, circuit behavior, and cross-domain debugging, with hybrid work patterns and a focus on development lifecycle coverage.