Senior Design Engineer : Custom Digital Hard Macros (Physical IP)

Arm Limited; Seattle (WA); Hybrid; USD 120,000 - 190,000; Full time

Job summary

Arm Limited is seeking a Design Engineer to contribute to digital hard macros across RTL, physical implementation, timing, and verification. You will work on custom and semi-custom macros, build automation flows, and participate in silicon validation, collaborating with SoC teams to optimize macro delivery.

The role emphasizes understanding of layout, circuit behavior, and cross-domain debugging, with hybrid work patterns and a focus on development lifecycle coverage.

Qualifications

• 2–5 years of experience in digital design or Physical IP.
• Strong RTL design fundamentals.
• Hands-on with synthesis, floorplanning, place-and-route, timing closure, and physical verification.
• Familiarity with Cadence Innovus, Tempus, Genus, or equivalents.
• Understanding of timing constraints, SDC, CDC, and multi-clock designs.
• Knowledge of transistor-level concepts and digital circuit operation.
• Experience with Verilog/SystemVerilog and scripting (Tcl or Python).
• Strong analytical, debugging, and teamwork skills.

Responsibilities

• Support design and implementation of custom and semi-custom digital hard macros.
• Develop and maintain RTL, timing constraints, implementation scripts, and automation flows.
• Execute synthesis, floorplanning, place-and-route, timing closure, physical verification, and signoff activities.
• Analyze and debug timing, power, congestion, DRC, LVS, and implementation issues.
• Review schematics and layout structures to understand macro operation and implementation tradeoffs.
• Support functional, gate-level, and mixed-signal simulation activities.
• Assist in characterization activities including timing, power, and functional model validation.
• Generate and validate macro deliverables including Liberty models, LEF abstracts, physical views, and integration collateral.
• Collaborate with AMS, DFT, verification, and SoC integration teams during development and product integration.
• Participate in silicon validation activities and support correlation of silicon behavior with pre-silicon expectations.
• Contribute to methodology improvements, scripting, and automation initiatives.

Skills

RTL design

Synthesis & PnR

Timing closure

Verilog/SystemVerilog

Scripting (Python/Tcl)

Debugging & analytics

Teamwork & communication

Tools

Cadence Innovus

Tempus

Genus

Job description

Role Overview

The Arm Solutions Engineering Physical IP group is building a team focused on the development of custom and semi-custom digital hard macros used across Arm CPU, GPU, NPU, and SoC products. These hard macros enable functionality that cannot be efficiently implemented using standard-cell methodologies alone, including power delivery, clocking structures, asynchronous interfaces, reliability mechanisms, and digital circuits interacting with analog and mixed-signal systems.

As a Design Engineer, you will contribute to the implementation and delivery of digital hard macros while developing a broad understanding of the complete macro development lifecycle. You will work across RTL, physical implementation, timing closure, simulation, characterization, and integration activities, gaining exposure to all aspects of Physical IP development.

The ideal candidate will possess strong implementation skills while also demonstrating curiosity and willingness to understand the underlying circuit, layout, simulation, and characterization aspects of macro development. Although not expected to be a specialist in analog design or characterization, the engineer should be capable of investigating issues across multiple abstraction levels and collaborating effectively with design, AMS, verification, and SoC integration teams.

Key Responsibilities

• Support design and implementation of custom and semi-custom digital hard macros.
• Develop and maintain RTL, timing constraints, implementation scripts, and automation flows.
• Execute synthesis, floorplanning, place-and-route, timing closure, physical verification, and signoff activities.
• Analyze and debug timing, power, congestion, DRC, LVS, and implementation issues.
• Review schematics and layout structures to understand macro operation and implementation tradeoffs.
• Support functional, gate-level, and mixed-signal simulation activities.
• Assist in characterization activities including timing, power, and functional model validation.
• Generate and validate macro deliverables including Liberty models, LEF abstracts, physical views, and integration collateral.
• Collaborate with AMS, DFT, verification, and SoC integration teams during development and product integration.
• Participate in silicon validation activities and support correlation of silicon behavior with pre-silicon expectations.
• Contribute to methodology improvements, scripting, and automation initiatives.

Required Skills & Experience

• 2-5 years of experience in digital design, physical implementation, Physical IP, or related semiconductor development.
• Good understanding of RTL design and digital design fundamentals.
• Hands-on experience with synthesis, floorplanning, place-and-route, static timing analysis, and physical verification.
• Familiarity with advanced implementation tools such as Cadence Innovus, Tempus, Genus, or equivalent.
• Understanding of timing constraints, SDC development, CDC concepts, and multi-clock designs.
• Working knowledge of transistor-level concepts, digital circuit operation, and custom layout fundamentals.
• Basic understanding of simulation methodologies including RTL, gate-level, and behavioral simulations.
• Familiarity with Liberty timing models and characterization concepts.
• Experience with Verilog/SystemVerilog and scripting languages such as Tcl or Python.
• Strong analytical, debugging, and problem-solving skills.
• Good communication and teamwork abilities.

Preferred Qualifications

• Exposure to hard-macro, memory, standard-cell, custom digital, or mixed-signal IP development.
• Experience at advanced process nodes.
• Exposure to low-power design methodologies and power-domain crossings.
• Understanding of metastability, asynchronous interfaces, and reliability concepts.
• Exposure to silicon validation or post-silicon debug activities

#LI-PS2

Our 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset

Accommodations at Arm

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [e-mail]. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.

Hybrid Working at Arm

Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.

Equal Opportunities at Arm

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.