Senior Digital Designer — FPGA/ASIC for EW & Radar

Analog Devices, Inc.; Chelmsford (MA); On-site; USD 117,000 - 161,000; Full time

Benefits offered by this job

Discretionary bonus

Medical, vision & dental

401k

Paid time off

Job summary

Analog Devices, Inc. is seeking a Senior Digital Design Engineer to design FPGA/ASIC RTL and schematic capture for EW, communications, and phased array radar systems. You will work with cross-functional teams through all lifecycle phases from research to production.

The role requires expertise in RTL, PCB, and high-speed design with 5+ years of relevant experience, and U.S. citizenship with ability to obtain a Secret Clearance. Competitive compensation and benefits are offered.

Qualifications

• PCB design, schematic capture, debug, and optimization.
• RTL design (Verilog/VHDL) with timing closure in large FPGAs.
• High-speed interface design and bring-up (e.g. 100 GigE, PCIe).

Responsibilities

• Develop FPGA-based designs for digital data and control paths.
• Design high-speed digital implementations for EW, RF, and phased array.
• Contribute to FPGA-centric digital hardware architecture and verification.

Skills

PCB design

RTL design

High-speed interfaces

Schematic capture

Education

Bachelor's or Master's degree in Electrical Engineering

Tools

Allegro

PADS

Job description

Analog Devices, Inc. is seeking a Senior Digital Design Engineer to design FPGA/ASIC RTL and schematic capture for EW, communications, and phased array radar systems. You will work with cross-functional teams through all lifecycle phases from research to production.

The role requires expertise in RTL, PCB, and high-speed design with 5+ years of relevant experience, and U.S. citizenship with ability to obtain a Secret Clearance. Competitive compensation and benefits are offered.